PIC18F2331 Datasheet, PDF(212/396 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC18F2331 Datasheet, PDF (212/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

◁

PIC18F2331/2431/4331/4431

TABLE 17-6: REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

Resets

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

IPR3

â

â

â

PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 ---1 1111

PIE3

â

â

â

PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 ---0 0000

PIR3

â

â

â

PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 ---0 0000

PTCON0

PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 0000 0000

PTCON1

PTEN PTDIR

â

â

â

â

â

â

PTMRL(1)

PWM Time Base (lower 8 bits)

PTMRH(1)

â

â

â

â PWM Time Base (upper 4 bits)

PTPERL(1) PWM Time Base Period (lower 8 bits)

PTPERH(1)

â

â

â

â PWM Time Base Period (upper 4 bits)

SEVTCMPL(1) PWM Special Event Compare (lower 8 bits)

SEVTCMPH(1)

â

â

â

â PWM Special Event Compare (upper 4 bits)

PWMCON0

â

PWMEN2 PWMEN1 PWMEN0 PMOD3(2) PMOD2 PMOD1 PMOD0

00-- ----

0000 0000

---- 0000

1111 1111

---- 1111

0000 0000

---- 0000

-101 0000

00-- ----

0000 0000

---- 0000

1111 1111

---- 1111

0000 0000

---- 0000

-101 0000

PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR

â

UDIS OSYNC 0000 0-00 0000 0-00

DTCON

FLTCONFIG

OVDCOND

OVDCONS

PDC0L(1)

PDC0H(1)

PDC1L(1)

PDC1H(1)

PDC2L(1)

PDC2H(1)

PDC3L(1,2)

PDC3H(1,2)

DTPS1 DTPS0 Dead Time A Value register

BRFEN FLTBS(2) FLTBMOD(2) FLTBEN(2) FLTCON

POVD7(2) POVD6(2) POVD5

POVD4 POVD3

POUT7(2) POUT6(2) POUT5

POUT4 POUT3

FLTAS

POVD2

POUT2

PWM Duty Cycle #0L register (lower 8 bits)

â

â PWM Duty Cycle #0H register (upper 6 bits)

PWM Duty Cycle #1L register (lower 8 bits)

â

â PWM Duty Cycle #1H register (upper 6 bits)

PWM Duty Cycle #2L register (Lower 8 bits)

â

â PWM Duty Cycle #2H register (Upper 6 bits)

PWM Duty Cycle #3L register (Lower 8 bits)

â

â PWM Duty Cycle #3H register (Upper 6 bits)

0000 0000 0000 0000

FLTAMOD FLTAEN 0000 0000 0000 0000

POVD1 POVD0 1111 1111 1111 1111

POUT1 POUT0 0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

--00 0000 --00 0000

Legend:

Note 1:

2:

- = Unimplemented, u = Unchanged. Shaded cells are not used with the power control PWM.

Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.

Unimplemented in PIC18F2X31 devices; maintain these bits clear. Reset values shown are for PIC18F4X31 devices.

DS39616B-page 210

Preliminary

ï£© 2003 Microchip Technology Inc.

▷