PIC18F2331 Datasheet, PDF (208/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.11.3 PWM OUTPUT PIN RESET STATES
The PWMPIN configuration bit determines the PWM
output pins to be PWM output pins or digital I/O pins,
after the device comes out of reset. If the PWMPIN con-
figuration bit is unprogrammed (default), the
PWMEN2:PWMEN0 control bits will be cleared on a
device Reset. Consequently, all PWM outputs will be
tri-stated and controlled by the corresponding PORT
and TRIS registers. If the PWMPIN configuration bit is
programmed low, the PWMEN2:PWMEN0 control bits
will be set as follows on a device Reset:
• PWMEN2:PWMEN0 = 101 if device has 8 PWM
pins (PIC18F4X31 devices)
• PWMEN2:PWMEN0 = 100 if device has 6 PWM
pins (PIC18F2X31 devices)
All PWM pins will be enabled for PWM output and will
have the output polarity defined by the HPOL and
LPOL configuration bits.
17.12 PWM Fault Inputs
There are two fault inputs associated with the PWM
module. The main purpose of the input fault pins is to
disable the PWM output signals and drive them into an
inactive state. The action of the fault inputs is
performed directly in hardware so that when a fault
occurs, it can be managed quickly and the PWMs
outputs are put into an inactive state to save the power
devices connected to the PWMs.
The PWM fault inputs are FLTA and FLTB, which can
come from I/O pins, the CPU or another module. The
FLTA and FLTB pins are active-low inputs so it is easy
to “OR” many sources to the same input.
The FLTCONFIG register (Register 17-8) defines the
settings of FLTA and FLTB inputs.
Note:
The inactive state of the PWM pins are
dependent on the HPOL and LPOL config-
uration bit settings, which defines the
active and inactive state for PWM outputs.
17.12.1 FAULT PIN ENABLE BITS
By setting the bits FLTAEN and FLTBEN in the
FLTCONFIG register, the corresponding fault inputs
are enabled. If both bits are cleared, then the fault
inputs have no effect on the PWM module.
17.12.2 MFAULT INPUT MODES
The FLTAMOD and FLTBMOD bits in the FLTCONFIG
register determine the modes of PWM I/O pins that are
deactivated when they are overridden by fault input.
FLTAS and FLTBS bits in the FLTCONFIG register give
the status of FaultA and FaultB inputs.
Each of the fault inputs have two modes of operation:
• Inactive Mode (FLTxMOD = 0)
This is a catastrophic Fault Management mode.
When the fault occurs in this mode, the PWM out-
puts are deactivated. The PWM pins will remain in
Inactivated mode until the fault is cleared (fault
input is driven high) and the corresponding fault
status bit has been cleared in software. The PWM
outputs are enabled immediately at the beginning
of the following PWM period, after Fault Status bit
(FLTxS) is cleared.
• Cycle-by-Cycle Mode (FLTxMOD = 1)
When the fault occurs in this mode, the PWM out-
puts are deactivated. The PWM outputs will
remain in the defined fault states (all PWM outputs
inactive) for as long as the fault pin is held low.
After the fault pin is driven high, the PWM outputs
will return to normal operation at the beginning of
the following PWM period, and the FLTS bit is
automatically cleared.
DS39616B-page 206
Preliminary
 2003 Microchip Technology Inc.