PIC18F2331 Datasheet, PDF (199/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 17-14:
DUTY CYCLE UPDATE TIMES IN UP/DOWN COUNTING MODE WITH DOUBLE
UPDATES
Duty cycle value loaded from buffer register
PWM output
PTMR Value
New values written to duty cycle buffer.
17.6.4 CENTER-ALIGNED PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in an
Up/Down Counting mode (see Figure 17-15). The
PWM compare output is driven to the active state when
the value of the Duty Cycle register matches the value
of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output
will be driven to the inactive state when the PWM time
base is counting upwards (PTDIR = 0) and the value in
the PTMR register matches the duty cycle value. If the
value in a particular Duty Cycle register is zero, then
the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the
output on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
or greater than the value in the PTPER register.
Note:
When the PWM is started in
Center-aligned mode, the period register
(PTPER) is loaded into the PWM Timer
register (PTMR) and the PTMR is
configured automatically to start
down-counting. This is done to ensure that
all the PWM signals don’t start at the same
time.
FIGURE 17-15: START OF CENTER-ALIGNED PWM
PTPER
Duty
Cycle
PTMR
Value
Period/2
0
Start of
first
PWM
Period
Duty Cycle
Period
Period
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 197