PIC18F2331 Datasheet, PDF (159/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
EQUATION 15-3:
log
 FOSC 
FPWM
PWM Resolution (max) = _log(2) bits
15.5.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the CCPR1L
register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 15-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
16
4
1
1
1
1
PR2 Value
FFh
FFh
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
10
10
10
8
7
6.58
TABLE 15-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF 0000 000x 0000 000u
PIR1
—
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PIE1
—
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
IPR1
—
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP -111 1111 -111 1111
TRISC PORTC Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
CCP1CON —
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON —
—
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 157