PIC18F2331 Datasheet, PDF (148/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 14-1:
T5CKI
TMR5CS
T5PS1:T5PS0
T5SYNC
TMR5ON
TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN)
Noise
Filter
1
FOSC/4
Internal
0
Clock
Prescaler
1, 2, 4, 8
2
1
Synchronize
detect
0
Sleep Input
Internal Data Bus
Timer5
On/Off
8
Special Event
Trigger Input
1
from IC1
Timer5 Reset
0
(external)
Set TMR5IF
Special Event
Trigger Output
Timer5 Reset
Reset
Logic
Special
Event
Logic
8
TMR5H
8
TMR5
TMR5L
8
TMR5
High Byte
16
Write TMR5L
Read TMR5L
Comparator
PR5
16
8
PR5L
PR5H
8
14.1 Timer5 Operation
Timer5 combines two 8-bit registers to function as a 16-
bit timer. The TMR5L register is the actual low byte of
the timer; it can be read and written to directly. The high
byte is contained in an unmapped register; it is read
and written to through TMR5H, which serves as a
buffer. Each register increments from 00h to FFh.
A second register pair, PR5H and PR5L, serves as a
period register; it sets the maximum count for the
TMR5 register pair. When TMR5 reaches the value of
PR5, the timer rolls over to 00h and sets the TMR5IF
interrupt flag. A simplified block diagram of the Timer5
module is shown in Figure 2-1.
Note:
The TIMER5 may be used as a general
purpose timer and as the time base
resource to the Motion Feedback module
(Input Capture or Quadrature Encoder
Interface).
Timer5 supports three configurations:
• 16-bit Synchronous Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
In Synchronous Timer configuration, the timer is
clocked by the internal device clock. The optional
Timer5 prescaler divides the input by 2, 4, 8, or not at
all (1:1). The TMR5 register pair increments on Q1.
Clearing TMR5CS (= 0) selects the internal device
clock as the timer sampling clock.
In Synchronous Counter configuration, the timer is
clocked by the external clock (T5CKI) with the optional
prescaler. The external T5CKI is selected by setting the
TMR5CS bit (TMR5CS = 1); the internal clock is
selected by clearing TMR5CS. The external clock is
synchronized to the internal clock by clearing the
T5SYNC bit. The input on T5CKI is sampled on every
Q2 and Q4 of the internal clock. The low to rise
transition is decoded on three adjacent samples and
DS39616B-page 146
Preliminary
 2003 Microchip Technology Inc.