PIC18F2331 Datasheet, PDF (190/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
REGISTER 17-4: PWMCON1: PWM CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
U-0
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR —
R/W-0 R/W-0
UDIS OSYNC
bit 7
bit 0
bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits
0000 =1:1 Postscale
0001 =1:2 Postscale
.
.
.
1111 =1:16 Postscale
bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit
1 = A special event trigger will occur when the PWM time base is counting downwards.
0 = A special event trigger will occur when the PWM time base is counting upwards.
bit 2 Unimplemented: Read as ‘0’.
bit 1 UDIS: PWM Update Disable bit
1 = Updates from duty cycle and period buffer registers are disabled.
0 = Updates from duty cycle and period buffer registers are enabled.
bit 0 OSYNC: PWM Output Override Synchronization bit
1 = Output overrides via the OVDCON register are synchronized to the PWM time base.
0 = Output overrides via the OVDCON register are asynchronous.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared x = bit is unknown
17.3.1 FREE RUNNING MODE
In the Free Running mode, the PWM time base
(PTMRL and PTMRH) will begin counting upwards until
the value in the Time Base Period Register, PTPER
(PTPERL and PTPERH), is matched. The PTMR regis-
ters will be reset on the following input clock edge and
the time base will continue counting upwards as long
as the PTEN bit remains set.
17.3.2 SINGLE-SHOT MODE
In the Single-shot mode, the PWM time base will begin
counting upwards when the PTEN bit is set. When the
value in the PTMR register matches the PTPER regis-
ter, the PTMR register will be reset on the following
input clock edge and the PTEN bit will be cleared by the
hardware to halt the time base.
17.3.3 CONTINUOUS UP/DOWN
COUNTING MODES
In continuous up/down counting modes, the PWM time
base counts upwards until the value in the PTPER
register matches with PTMR. On the following input
clock edge, the timer counts downwards. The PTDIR
bit in the PTCON1 register is read-only and indicates
the counting direction. The PTDIR bit is set when the
timer counts downwards.
Note:
When the PWM timer is enabled in
Up/Down Count mode, during the first half
of the first period of the up/down counting
modes, the PWM outputs are kept
inactive. By doing this, PWM pins will
output garbage duty cycle due to unknown
value in the PTMR registers.
17.3.4 PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4) has prescaler
options of 1:1, 1:4, 1:16 or 1:64. These are selected by
control bits PTCKPS<1:0> in the PTCON0 register. The
prescaler counter is cleared when any of the following
occurs:
• Write to the PTMR register
• Write to the PTCON (PTCON0 or PTCON1)
register
• Any device Reset
Note: The PTMR register is not cleared when
PTCON is written.
Table 17-1 shows the minimum PWM frequencies that
can be generated with the PWM time base and the
prescaler. An operating frequency of 40 MHz
(FCYC = 10 MHz) and PTPER = 0xFFF is assumed in
the table. The PWM module must be capable of gener-
ating PWM signals at the line frequency (50 Hz or
60 Hz) for certain power control applications.
DS39616B-page 188
Preliminary
 2003 Microchip Technology Inc.