PIC18F2331 Datasheet, PDF (293/396 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 23-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
n
Branch if Carry
1 (2)
1110 0010 nnnn nnnn None
BN
n
Branch if Negative
1 (2)
1110 0110 nnnn nnnn None
BNC
n
Branch if Not Carry
1 (2)
1110 0011 nnnn nnnn None
BNN
n
Branch if Not Negative
1 (2)
1110 0111 nnnn nnnn None
BNOV
n
Branch if Not Overflow
1 (2)
1110 0101 nnnn nnnn None
BNZ
n
Branch if Not Zero
2
1110 0001 nnnn nnnn None
BOV
n
Branch if Overflow
1 (2)
1110 0100 nnnn nnnn None
BRA
n
Branch Unconditionally
1 (2)
1101 0nnn nnnn nnnn None
BZ
n
Branch if Zero
1 (2)
1110 0000 nnnn nnnn None
CALL
n, s Call subroutine 1st word
2
1110 110s kkkk kkkk None
2nd word
1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer
1
0000 0000 0000 0100 TO, PD
DAW
— Decimal Adjust WREG
1
0000 0000 0000 0111 C, DC
GOTO
n
Go to address 1st word
2
1110 1111 kkkk kkkk None
2nd word
1111 kkkk kkkk kkkk
NOP
— No Operation
1
0000 0000 0000 0000 None
NOP
— No Operation
1
1111 xxxx xxxx xxxx None
4
POP
— Pop top of return stack (TOS) 1
0000 0000 0000 0110 None
PUSH
— Push top of return stack (TOS) 1
0000 0000 0000 0101 None
RCALL n
Relative Call
2
1101 1nnn nnnn nnnn None
RESET
Software device Reset
1
0000 0000 1111 1111 All
RETFIE s
Return from interrupt enable 2
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k
Return with literal in WREG 2
0000 1100 kkkk kkkk None
RETURN s
Return from Subroutine
2
0000 0000 0001 001s None
SLEEP — Go into Standby mode
1
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that
all program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
 2003 Microchip Technology Inc.
Preliminary
DS39616B-page 291