82443LX Datasheet, PDF (99/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
4.4.1.1.
Error Detection and Correction
ECC is an optional data integrity feature provided by PAC. The feature provides single-error correction,
double-error detection, and detection of all errors confined to a single nibble (SEC-DED-S4ED) for the DRAM
memory subsystem. Additional features are provided that enable software-based system management
capabilities.
• ECC Checking and Correction. When enabled, the ECC mechanism allows a detection of single-bit and
multiple-bit errors and recovery of single-bit errors. During DRAM read operations, a full QWord of data is
always transferred from DRAM to PAC, regardless of the size of the originally requested data and type of
selected memory protection. Both 64-bit data and 8-bit ECC code are transferred simultaneously from
DRAM to PAC. The ECC checking logic in PAC generates a new ECC code for the received 64-bit data
and compares it with received ECC code. If a single-bit error is detected the ECC logic generates a new
“recovered” 64-bit data with a pattern which corresponds to the originally received 8-bit ECC protection
code. Note that recovered data is transferred from PAC to the original requester (Host, A.G.P. or PCI
interface), but PAC does not initiate the DRAM write cycle to fix the error.
• Error Reporting. For single-bit error indication, the SEF flag is set by PAC in the ERRSTS0 (Error Status
0) Register, along with the row number associated with the first single-bit error. Similarly, for multiple bit
error indication, the MEF flag is set in the ERRSTS0 Register along with the row number associated with
the first multiple bit error. After logging the first error in both single-bit and multiple-bit error cases, the
register is locked until the software writes to the respective flags and clears the SEF and MEF bits. This
error condition is normally reported via ECCERR# signal and it can also be reported to the system via the
SERR# mechanism. This functionality is controlled by the ERRCMD (Error Command) register.
• DRAM Scrubbing. The DRAM (if the root-cause of the error is a DRAM array) will still contain faulty data
which will cause the repetition of error detection and recovery for the subsequent accesses to the same
location. However, to prevent the accumulation of the single-bit errors which may result in an
unrecoverable multi-bit error, the system software can provide a “scrubbing” functionality. After a single-
bit correctable ECC error is reported, either via a hardware mechanism (ECCERR# signal that ties to an
SMI or a regular interrupt, or the SERR# signal which typically causes an NMI) or by a software
mechanism (periodic polling of the ERRSTS0 Register), a DRAM “scrubbing” software routine should
initiate reads followed with writes of the same data to the locations at which the single-bit error occurred.
Read of the data will result in a corrected 64-bit value which will be written back to establish the correct
value within the DRAM array. Since it is not critical to fix the single-bit error right away, the “scrubbing”
routine can be run as a part of the lowest priority task in the multitasking operating system environment,
and hence, will not impose a significant overhead in the system. Note that information in the ERRSTS0
Register can be used later on to point to a faulty DRAM DIMM if the single-bit errors constantly occur
during access to that DIMM.
Multi-bit uncorrectable errors are fatal system errors and will cause PAC to assert the SERR# signal if bit 1 of
the ERRCMD register is a 1. SERR# will then activate NMI. When an uncorrectable error is detected, PAC
will latch the row # where the error occurred in the ERRSTS1 Register.
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