82443LX Datasheet, PDF (28/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 7. Signals During Reset
Signal Name
GNT[4:0]#
IRDY#
State
Tri-state
Tri-state
Signal Name
RCSA[7:6]#/MAB[3:2]
SRAS3#/MAB5
State
High / —
High / —
PERR#
Tri-State
SCAS3#/MAB4
High / —
PHLD#
PHLDA#
—
Tri-state
WE[3:0]#
SRAS[2:0]#
High
High
PLOCK#
Tri-state
SCAS[2:0]#
High
REQ[4:0]#
SERR#
—
Tri-state
MD[63:0]
Low
MECC[7:0]
Low
STOP#
TRDY#
Tri-state
Tri-state
CKE
Strapped Value
Miscellaneous Signals
WSC#
High
ECCERR#
Low
A.G.P. Signals and A.G.P. Sideband Signals
CRESET
Low
GAD[31:0]#
Low
GC/BE[3:0]#
Low
GPAR
Low
NOTES:
1. If MECC was sampled low during the rising edge of PWROK, PAC is responsible for driving A7# active at
least 6 host clocks prior to the CPURST# active-to-inactive transition. PAC drives A7# inactive 4 host
clocks after the rising edge of CPURST#. If MECC was sampled high during the rising edge of PWROK,
then A7# will not be driven.
2. INIT is driven active (low) for a software generation of BIST.
3. BREQ0# must stay asserted (low) for a minimum of 2 host clocks after the rising edge of CPURST#. PAC
then releases (tri-states) the BREQ0# signal.
4. “” is “don’t care.”
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