82443LX Datasheet, PDF (84/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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combining the several back-to-back Partial write transactions (internal to the CPU) into a Line write
transaction on the CPU bus, the performance of frame buffer accesses is greatly improved. To this end, the
CPU supports the WC memory. Writes to WC memory can be buffered and combined in the processor’s write
combining buffers (WCB). The WCB is flushed after executing a serializing, locked, I/O instruction, or the
WCB is full (32 bytes). To extend this capability to the current drivers, it is necessary to set up the linear
frame buffer address range to be WC memory type. This can be done by programming the MTRR registers in
the CPU. Note that for dual processors, the MTRR must be programmed identically.
If non-contiguous bytes are written to the WCB, upon eviction, a series of write partial transactions will be
performed. If a series of contiguous writes are written to a WC memory region (such as a copy) a series of
write line transactions will be performed. PAC further optimizes this by providing write combining for CPU-to-
PCI or CPU-to-A.G.P. write transactions. If the target of CPU writes is the PCI memory, data is combined and
sent to the PCI bus as a single write burst. The same concept applies to CPU writes to A.G.P. memory. The
WC writes that target DRAM are handled as regular main memory writes.
Note that the application of the WC memory attribute is not limited to the frame buffer and that PAC
implements combining for any CPU-to-PCI or CPU-to-A.G.P. posted write, independent of the WC memory
attribute.
The PAC host bridge allows an additional level of concurrency for CPU Write accesses to WC space on PCI
during the time when the I/O bridge (i.e., PIIX4) prevents posting of the writes (via PHLD#/PHLDA# protocol)
destined to UC (uncacheable space) located on PCI or ISA.
The PAC defers Stop Grant Acknowledge cycles generated by the processor in response to STPCLK# being
asserted. The PAC completes the Stop Grant Acknowledge on the PCI bus and then issues a Defer Reply
Transaction on the host bus to complete the Stop Grant Acknowledge cycle back to the processor. Once the
Stop Grant Acknowledge has been completed on the PCI bus, there may be a delay in issuing the Defer
Reply Transaction caused by high priority A.G.P. traffic. This delay prevents the use of clock throttling as
defined in the 82371AB PIIX4 with the PAC. 440LX system designers should not enable manual (BIOS
control) or thermal (THRM# pin active) clock throttling as defined in 82371AB PIIX4 datasheet.
4.3. DRAM Interface
The 82443LX integrates a main memory DRAM controller that supports a 72-bit memory data interface (64-bit
memory data plus 8 ECC bits). The DRAM types supported are Extended Data Out (EDO), and Synchronous
DRAM (SDRAM). PAC generates the Row Address Strobe/Chip Selects (RCSA# and RCSB#), Column
Address Strobe/Data Mask (CDQA# and CDQB#), SCAS#, SRAS#, CKE, WE#, and Memory Addresses
(MA) for the DRAM array. For CPU/PCI/A.G.P.-to-DRAM cycles, the address and data flows through PAC.
PAC generates data on the MD and MECC busses for writes, and accepts data on these busses during
reads. PAC also asserts ECCERR# in the event of a single-bit correctable or multi-bit uncorrectable error, if
enabled. The PAC DRAM interface operates synchronously to the CPU clock. The DRAM controller interface
is fully configurable through a set of control registers.
PAC supports industry standard 64/72-bit wide DIMM modules with EDO or SDRAM devices. Fourteen
memory address signals (MAx[13:0]) allow PAC to support a wide variety of commercially available DIMMs.
Both symmetrical and asymmetrical addressing are supported. Eight RCS# lines permit up to eight 64-bit
wide rows of DRAM. For write operations of less than a QWord, PAC will either perform a byte-wise write
(non ECC protected configuration) or a read-modify-write cycle by merging the write data on a byte basis with
the previously read data (ECC configurations). PAC supports 50 ns and 60 ns EDO DRAMs, 66-MHz
SDRAMs with CL2 and CL3, and supports both single and double-sided DIMMs.
Refresh functionality (DRAM refresh rate is 1 refresh/15.6 µs) is provided and there is a seven deep refresh
queue with three levels of request priority. The refresh queue can be disabled, resulting in a high priority
refresh request for every time-out. If the queue is enabled, the refresh request priority will work as follows:
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