82443LX Datasheet, PDF (68/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.4.7. BCC1—BASE CLASS CODE REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
0Bh
06h
Read Only
This register contains the device programming interface information related to the Base Class Code definition
for PAC device 1.
Bit
Description
7:0 Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for PAC
device #1.
06h=Indicates a bridge device.
3.4.8. HDR1—HEADER TYPE REGISTER (DEVICE 1)
Offset:
Default:
Access:
0Eh
01h
Read Only
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Description
7:0 Header Type (HEADT). This read only field always returns 01h when read. Writes have no effect.
3.4.9. PBUSN—PRIMARY BUS NUMBER REGISTER—DEVICE #1
Offset:
Default:
Access:
Size:
18h
00h
Read Only
8 bits
This register identifies that the “virtual” PCI-PCI bridge is connected to bus #0.
Bit
Description
7:0 Bus Number. The value of this 8-bit register is always 00h.
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