82443LX Datasheet, PDF (82/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
4.1.5.2.
A.G.P. Interface Decode Rules
Cycles Initiated Using PCI Protocol
Accesses between the A.G.P. port and the PCI port are limited to memory writes using the A.G.P. FRAME#
protocol. All A.G.P. memory write cycles will be claimed by PAC. If the addresses are not within the main
DRAM range or Graphics Aperture range, the cycle will be forwarded to the PCI bus.
When the A.G.P. master issues a memory read transaction using FRAME# semantics, the cycle will be
claimed by PAC only if the address is within main DRAM range or Graphics Aperture Range. All other
memory read requests will be master-aborted as a consequence of PAC not responding to a transaction.
If the agent on A.G.P. issues an I/O, Configuration or Special Cycle transaction, PAC will not respond and the
cycle will result in a master-abort.
Cycles Initiated Using A.G.P. Protocol
All cycles initiated using A.G.P. PIPE# or SBA protocol must reference main memory (i.e., main DRAM
address range or Graphics Aperture range). If a cycle is outside of the main memory range, then it will
terminate as follows:
• Reads: return random value.
• Writes: terminated internally without affecting any buffers or main memory.
4.1.5.3.
Legacy VGA and MDA Ranges
The legacy VGA memory range A0000h–BFFFFh is mapped either to PCI or A.G.P. depending on the
programming of the BCTRL1 and PCICMD1 configuration registers. The same registers control mapping of
VGA I/O address ranges. VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to
3BBh and 3C0h to 3DFh (inclusive of ISA address aliases—A[15:10] are not decoded).
The legacy MDA range is not always forwarded with the VGA range. It may be necessary to forward MDA to
PCI (for eventual forwarding to ISA) while forwarding VGA to A.G.P. This would be necessary if an ISA MDA
adapter and an A.G.P. VGA adapter were in the system.
Table 13 explains the interaction of the ISA Enable, VGA Enable, MDA Enable bits and IOBASE/IOLIMIT
registers:
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