82443LX Datasheet, PDF (91/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
4.3.1.1.
Configuration Mechanism for DIMMs
PAC DRAM Controller uses the Serial Presence Detect (SPD) mechanism for memory array configuration, as
defined in the JEDEC 168-pin DIMM Standard Specification.
NOTE
It is very difficult to program the 82443LX DRAM Timing Register (Register 58h, Device #0) and the
DRAM Buffer Strength register (Register 6C–6Fh, Device #0) without information garnered using Serial
Presence Detect (SPD). Thus, support for SPD in a PAC memory array is required.
The system BIOS must program the DRAM size, type, timing, and buffer strength registers in the 82443LX. It
gathers this information by the Serial Presence Detect (SPD) mechanism.
DRAM Configuration is performed by the BIOS, which follows these six steps:
1. The system BIOS must loop through the rows of memory (8 rows for Memory Configuration #1, 6 rows for
Memory Configuration #2) reading Serial Presence Detect (SPD) data. This will allow it to determine
whether each DIMM in the array is single or double sided. The system BIOS must also determine the
type of memory contained in each row, and set the DRAM Type registers accordingly (DRT—Device #0,
Register 55–56h). Also, note that, at this time, system BIOS should determine the SLOWEST CAS
Latency of all of the available SDRAM DIMMs in the array.
2. BIOS must next loop through the rows of memory, initialize and configure each row of SDRAM. Note that
the SDRAM DIMMs will ALL be programmed to either CAS Latency=2 or CAS Latency=3; whichever is
the SLOWEST DIMM found in step 1.
3. BIOS must next loop through the rows of memory, reading SPD data to determine the DRAM size. The
DRB’s (DRB[7:0]—device #0, register 60–67h) can now be set. Additionally, several different bytes of
SPD data can be read to determine the timing values to be used when programming the memory timing
register (DRAMT—device #0, register 58h) and to determine if ECC can be enabled (if all available
DIMM’s support ECC).
4. BIOS must next program the Memory Buffer Strength Control Register (MBSC—device #0, register
6C–6Fh). To program this register properly, additional bytes of SPD data must be read for each row of
memory.
5. BIOS can use the data found in step 3 to program the DRAM timing register (DRAMT—device #0,
register 58h).
6. Lastly, if ALL of the DIMM’s in the array support ECC, then ECC should be enabled in PAC.
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