82443LX Datasheet, PDF (38/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.3.5. RID—REVISION IDENTIFICATION REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
08h
See Stepping Information.
Read Only
This register contains the revision number of PAC Device 0. These bits are read only and writes to this
register have no effect.
Bit
Description
7:0 Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for PAC Device 0.
03h=Hardwired
3.3.6. SUBC—SUB-CLASS CODE REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
0Ah
00h
Read Only
This register contains the Sub-Class Code definition for PAC.
Bit
7:0 Sub-Class Code (SUBC).
00h=Host Bridge.
Description
3.3.7. BCC—BASE CLASS CODE REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
0Bh
06h
Read Only
This register contains the Base Class Code definition for PAC.
Bit
7:0 Base Class Code (BASEC).
06h=Bridge device.
Description
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