82443LX Datasheet, PDF (21/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Table 3. PCI Interface Signals
Name
Type
Description
C/BE[3:0]# I/O PCI Command/Byte Enable: The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
PCI Bus command encoding and types are listed below.
C/BE[3:0]# Command Type
C/BE[3:0]# Command Type
0000
0001
0010
0011
0100
0101
0110
0111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
1000
1001
1010
1011
1100
1101
1110
1111
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Reserved (Dual Addr Cyc)
Memory Read Line
Memory Write and Invalidate
PAR
I/O PCI Parity: A single parity bit is provided over AD[31:0] and C/BE[3:0]. Even parity is
generated across AD[31:0] and C/BE[3:0]#.
PERR#
I/O PCI PCI Parity Error: Pulsed by an agent receiving data with bad parity one clock after
PAR is asserted. PAC generates PERR# active if it detects a parity error on the PCI
bus and the PERR# Enable bit in the PCICMD register is set.
PLOCK# I/O PCI Lock: Used to establish, maintain, and release resource locks on PCI.
TRDY# I/O PCI Target Ready: Asserted when the target is ready for a data transfer.
SERR#
I/O PCI System Error: PAC asserts this signal to indicate an error condition. The SERR#
assertion by the PAC is enabled globally via the SERRE bit of the PCICMD register.
SERR# is asserted under the following conditions:
1. PAC asserts SERR# when it is configured for ECC operation, ECC error
signaling via the SERR# mechanism is enabled via the ERRCMD_control
register, and a single bit (correctable) ECC error or multiple bit (non-correctable)
ECC error occurred.
2. PAC asserts SERR# for one clock when it detects a target abort during PAC
initiated PCI cycle.
3. PAC can also assert SERR# when a PCI parity error occurs during the address
phase if Parity Error Enable (register 04h, bit 6), SERR Enable (register 04h, bit
8), and SERR# on PCI Parity Error (register 90h, device 3) are set.
4. PAC can assert SERR# when it samples PERR# asserted on the PCI bus. This
capability is controlled by bit 3 of the ERRCMD register.
5. PAC can assert SERR# when it detects assertion of G-SERR# input signal. This
capability is controlled by bit 5 of the ERRCMD register.
STOP# I/O PCI Stop: Asserted by the target to request the master to stop the current transaction.
PCLKIN
I PCI Clock In: See Clocks, Reset, and Miscellaneous Signals Section.
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