82443LX Datasheet, PDF (85/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
• The high priority refresh request asserts when the queue is full and takes priority over all other DRAM
operations.
• The medium priority request asserts when 4 queue slots are filled and takes priority over all other DRAM
operations except A.G.P. expedites.
• Finally, the low priority request asserts when 1 queue slot is filled and only executes if there are no other
DRAM operations in progress or pending.
The DRAM interface of PAC is configured by the Aperture Base Configuration Register, Graphics Aperture
Remapping Table Base Register, A.G.P. Control Register, PAC Configuration Register, Memory Buffer
Strength Control Register, DRAM Control Register, DRAM Timing Register, DRAM Row Type Register, and
DRAM Row Boundary (DRB) Registers.
The DRAM configuration registers control the DRAM interface to select EDO DRAM or SDRAM DRAMs, RAS
timings, and CAS rates. The eight DRB registers define the size of each row in the memory array, enabling
PAC to assert the proper RCSA#/RCSB# line (Row Address A & B#/Chip Select#), for accesses to the array.
PAC closes the page when there are no more DRAM requests and the DRAM arbiter (conceptual) enters the
IDLE state. PAC does, however, hold the last accessed memory page open for PCI or A.G.P.-to-DRAM read
accesses until there is a page miss or refresh.
Seven Programmable Attribute Map (PAM) registers are used to specify the PCI enable, and read/write
status of the memory space between 640 KB and 1 MB. Each PAM Register defines a specific address area
enabling the system to selectively mark specific memory ranges as read only, write only, read/write, or
disabled. PAC supports one fixed memory hole selectable as either from 512 KB to 640 KB or from 15 MB to
16 MB in main memory. The SMRAM memory space is controlled by the SMRAM control register. This
register selects if the SMRAM space is enabled, opened, closed, or locked.
NOTE
These MECC signals must be low when RSTIN# is negated. If CKE is low (clock disabled), SDRAM
DIMMs could continue to drive the MECC lines through reset (the lines will stay in their existing state
when CKE is low). RSTIN# should be inverted and tied to the output enable of the tri-state buffer that
drives the CKE signal to the DIMMs. Thus, the tri-state buffer will tri-state and the pull-up resistors will
pull CKE high (and the DIMMs can finish the cycle). This causes the SDRAM DIMMs to tri-state.
The MECC signals must be low when RSTIN# is negated. RSTIN# should be inverted and tied to the
OE# pin on all DIMM sockets. If the DIMMs continue to drive the ECC lines at reset, this ensures that
the signals are not being driven when RSTIN# is negated. It is possible that will keep CAS# asserted
during reset and therefore EDO DIMMs will continue to drive their ECC lines.
4.3.1. DRAM ORGANIZATION AND CONFIGURATION
In the following discussion the term row refers to a set of memory devices that are simultaneously selected
by a RCS[A,B]#/CS# signal. PAC supports a maximum of 8 rows of memory in memory configuration #1, or
6 rows in memory configuration #2. A row may be composed of one or more discrete DRAM devices (e.g.,
planar motherboard memory), or single-sided or double-sided DIMM modules arranged in sockets on the
motherboard.
NOTE
The main DRAM design target is EDO/SDRAM configuration using 168-pin unbuffered DIMMs.
85