82443LX Datasheet, PDF (15/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Table 1. Host Interface Signals
Name
Type
Description
HTRDY#
I/O GTL+ Host Target Ready: Indicates that the target of the CPU bus transaction is able
to enter the data transfer phase.
INIT#
O LVTTL Initialization. This is the output signal generated by the PAC after a CPU
shutdown bus cycle, or after a soft reset is initiated by writing to the reset
control register.
RS[2:0]# I/O GTL+ Response Signals: Indicates type of response according to the following table:
RS[2:0]
000
001
010
011
Response type
Idle state
Retry response
Deferred response
Reserved
RS[2:0]
100
101
110
111
Response type
Hard Failure
No data response
Implicit Writeback
Normal data response
HCLKIN
I
LVTTL
(2.5V)
Host Clock In: See Clocks, Reset, and Miscellaneous Signals Section.
NOTES:
All of the signals in the host interface are described in the Pentium II Processor data book. The preceding
table highlights PAC specific uses of these signals.
2.1.2. DRAM INTERFACE SIGNALS
The PAC DRAM Controller supports two different memory configurations, which are selected during Reset via
a strapping on the CKE pin. Configuration #1 is the large memory array. Configuration #2 is the small
memory array.
Signal
RCSA[5:0]#
Table 2. DRAM Interface Signals
Type
Description
O Row Address Strobe 5-0 (EDO): These signals are used to latch the row
LVTTL address into the memory array. Each signal is used to select one DRAM row.
These signals drive the DRAM array directly without any external buffers.
Chip Select 5-0 (SDRAM): For the memory row configured with SDRAM, these
pins perform the function of selecting the particular SDRAM components during
the active state.
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
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