82443LX Datasheet, PDF (25/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Table 4. A.G.P. Signals
Name
Type
Description
GPAR
I/O
A.G.P.
A.G.P. Parity: A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
Even parity is generated across AD[31:0] and C/BE[3:0]#. Not used on A.G.P.
sideband transactions.
NOTES:
1. A.G.P. Addressing Signals. This section of the table contains two mechanisms to enqueue requests by
the A.G.P. master. Note that the master can only use one mechanism. When PIPE# is used to enqueue
addresses the master is not allowed to enqueue addresses using the SB bus. For example, during
configuration time, if the master indicates that it can use either mechanism, the configuration software will
indicate which mechanism the master will use. Once this choice has been made, the master continues to
use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This
change of modes is not a dynamic mechanism, but rather a static decision when the device is first being
configured after reset.
2. A.G.P. FRAME# Protocol Signals (similar to PCI): These signals, for the most part, are redefined when
used in A.G.P. transactions using A.G.P. sideband protocol extensions. For transactions on the A.G.P.
interface using FRAME# protocol, these signals preserve PCI semantics. The exact role of these signals
during A.G.P. sideband transactions is defined in this section of the table.
a. RSTIN# is used to reset A.G.P. interface logic within the PAC. The A.G.P. agent will use a system
PCIRST# signal provided by the I/O bridge (i.e., PIIX4) as an input to reset its internal logic.
b. LOCK# signal is not supported on the A.G.P. interface (even for FRAME# protocol operations).
c. Pins During A.G.P. FRAME# protocol Transactions. Signals described in a previous table behave
according to PCI 2.1 specifications when used to perform A.G.P. FRAME# protocol transactions on
the A.G.P. Interface.
2.1.5. CLOCKS, RESET, AND MISCELLANEOUS SIGNALS
Name
HCLKIN
PCLKIN
GTLREF
AGPREF
VTT
REF5V
Table 5. Clocks, Reset, Reference Voltage, and Miscellaneous Signals
Type
Description
I
LVTTL
(2.5V)
Host Clock In: This pin receives a buffered host clock. This clock is used by all
of the PAC logic that is in the Host clock domain.
I
LVTTL
PCI Clock In: This is a buffered PCI clock reference that is synchronously
derived by an external clock synthesizer component from the host clock (divide-
by-2). This clock is used by all of the PAC logic that is in the PCI clock domain.
I
GTL+ Reference Voltage: This is the reference voltage derived from the
termination voltage to the pull-up resistors and determines the noise margin for
the signals. This signal goes to the reference input of the GTL+ sense amp on
each GTL+ input or I/O pin.
I
A.G.P. Reference Voltage.
I
GTL+ Termination Reference Voltage.
I
5V Reference Voltage: This reference pin provides a reference voltage for the
5V safe PCI Bus interface.
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