82443LX Datasheet, PDF (45/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
Bit
Description
6 SDRAM CAS Latency (SCLT). This bit defines the CLT timing parameter of SDRAM expressed
in 66-MHz clocks.
1=2 clocks
0=3 clocks (default)
5 SDRAM RAS Precharge Time (SRPT). This bit defines the RAS precharge requirements for the
SDRAM memory type in 66-MHz clocks.
1=2 clocks
0=3 clocks (default)
4 EDO DRAM Read Burst Timing (DRBT). The DRAM read burst timings are controlled by the
DRBT field. Slower rates may be required in certain system designs to support loose layouts or
slower memories. Most system designs will be able to use one of the faster burst mode timings.
The timing used depends on the type of DRAM on a per-row basis, as indicated by the DRT
register.
1=Read Rate is x222
0=Read Rate is x333 (default)
3 EDO DRAM Write Burst Timing (DWBT). The DRAM write burst timings are controlled by the
DWBT field. Slower rates may be required in certain system designs to support loose layouts or
slower memories. Most system designs will be able to use one of the faster burst mode timings.
The timing used depends on the type of DRAM on a per-row basis, as indicated by the DRT
register.
1=Write Rate is x222
0=Write Rate is x333 (default)
2 EDO RAS Precharge Time (RPT). This bit defines the RAS precharge requirements for the EDO
memory type in 66-MHz clocks.
1=3 clocks.
0=4 clocks (default)
1 EDO RAS to CAS Delay (RCD). This bit defines the delay in assertion of CAS# (SCAS#) from
assertion of RAS# (SRAS#) in 66-MHz clocks.
1=2 clock delay.
0=3 clock delay (default)
0 MA Wait State (MAWS). This bit selects FAST or SLOW MA bus timing. Note that SLOW timing
is equal to FAST +1, in terms of clock numbers for EDO. For SDRAM, FAST timing means zero
MA wait state. This setting will enable PAC to support a Single Clock Command Mode. SLOW
means one MA wait state, which forces PAC to support the normal operation (one command per
two clocks).
1=FAST
0=SLOW (default)
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