82443LX Datasheet, PDF (67/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.4.4. PCISTS1—PCI-PCI STATUS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
06–07h
02A0h
Read Only, Read/Write Clear
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the primary
side of the “virtual” PCI-to-PCI bridge in PAC.
Bit
Description
15 Reserved.
14 Signaled System Error (SSE1)—R/WC.
1=When PAC asserts the SERR# signal due to error condition on the A.G.P. side (i.e.,
GSERR# activated), this bit is also set to 1. Software sets SSE1 to 0 by writing a 1 to
this bit.
13:0 Reserved.
3.4.5. RID1—REVISION IDENTIFICATION REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
08h
03h
Read Only
This register contains the revision number of PAC Device 1. These bits are read only and writes to this
register have no effect. This value is hardwired to 03h.
Bit
Description
7:0 Revision Identification Number. This is an 8-bit value that indicates the revision identification
number for PAC Device 1.
3.4.6. SUBC1—SUB-CLASS CODE REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
0Ah
04h
Read Only
This register contains the device programming interface information related to the Sub-Class Code definition
for PAC device 1.
Bit
Description
7:0 Sub-Class Code (SUBC1). This is an 8-bit value that indicates the category of bridge for PAC
device #1.
04h=Indicate a PCI-to-PCI Bridge.
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