82443LX Datasheet, PDF (49/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
Row Boundary Address
INTEL 82443LX (PAC)
RAS7#
RAS6#
RAS5#
RAS4#
RAS3#
RAS2#
RAS1#
RAS0#
DMM-3 Back
DMM-3 Front
DMM-2 Back
DMM-2 Front
DMM-1 Back
DMM-1 Front
DMM-0 Back
DMM-0 Front
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
CAS7# CAS5# CAS3# CAS1#
CAS6# CAS4# CAS2# CAS0#
DRB_REG
Figure 2. DIMMs and Corresponding DRB Registers
The following 2 examples describe how the DRB Registers are programmed for cases of single-sided and
double-sided DIMMs on a motherboard with 4 DIMM sockets.
Example #1 Single-sided DIMMs. Assume a total of 16 MB of DRAM are required using single-sided 1 MB x
64 DIMMs. Since the memory array is 64-bits wide, two DIMMs are required.
DRB0=01h
DRB1=01h
DRB2=02h
DRB3=02h
DRB4=02h
DRB5=02h
DRB6=02h
DRB7=02h
populated (1 DIMM, 8 MB this row)
empty row (empty side of single-sided DIMM)
populated (1 DIMM, 8 MB this row)
empty row (empty side of single-sided DIMM)
empty row (empty socket)
empty row (empty socket)
empty row (empty socket)
empty row (empty socket)
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