82443LX Datasheet, PDF (61/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
a) BIST Mode Hard Reset
CPURST#
INIT#
1 msec = 65,536 clks
1 msec = 65,536 clks
+4 clks
b) Soft Reset
INIT#
4 clks
BIST
Figure 3. Soft Reset and BIST Hard Reset Timing
3.3.28. ACAPID—A.G.P. CAPABILITY IDENTIFIER REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
A0–A3h
00100002h
Read Only
This register provides a standard identifier for A.G.P. capability.
Bit
Description
31:24 Reserved.
23:20 Major A.G.P. Revision Number. This field provides a major revision number of the A.G.P.
specification to which this version of PAC conforms. This number is hardwired to value of “0001”
(i.e., implying Rev 1.x)
19:16
Minor A.G.P. Revision Number. This field provides a minor revision number of the A.G.P.
specification to which this version of PAC conforms. This number is hardwired to value of “0000”
(i.e., implying Rev x.0). Together with major revision number this field identifies PAC as an A.G.P.
REV 1.0 compliant device.
15:8 Next Capability Pointer. A.G.P. capability is the first and the last capability described with this
mechanism, and therefore, these bits are hardwired to 0 to indicate the end of the capability
linked list.
7:0 A.G.P. Capability ID. This field identifies the linked list item as containing A.G.P. registers. This
field has a value of 0010b assigned by the PCI SIG.
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