82443LX Datasheet, PDF (24/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 4. A.G.P. Signals
Name
Type
Description
GIRDY#
I/O A.G.P.
A.G.P. Initiator Ready: For A.G.P. Frame# protocol transactions, this signal is
asserted when the initiator is ready for a data transfer. It indicates that the
A.G.P. compliant master is ready to provide all write data for the first block of a
sideband transaction.
GTRDY#
I/O A.G.P.
A.G.P. Target Ready: For A.G.P. Frame# protocol transactions, this signal is
asserted when the target is ready for a data transfer. It indicates the A.G.P.
compliant target is ready to provide read data for the first block of a sideband
transaction .
GSTOP# I/O A.G.P. A.G.P. Stop: Asserted by the target to request the master to stop the current
transaction.
GDEVSEL#
I/O A.G.P.
A.G.P. Device Select: Assertion indicates that a A.G.P. target device has
decoded its address as the target of the current access. PAC asserts DEVSEL#
if the current access is:
• within Main Memory
• resides on the PCI interface
As an input, this signal indicates whether a device on the bus has been
selected.
GPERR# I/O A.G.P. A.G.P. Parity Error: Pulsed by an agent receiving data with bad parity one
clock after GPAR is asserted.
GSERR#
I
A.G.P.
A.G.P. System Error: May be used by A.G.P. master to report a catastrophic
error. Routed internally within PAC to the primary PCI bus SERR# signal (direct
connection between GSERR# 66-MHz signal and SERR# 33-MHz signal is not
possible).
GREQ#
I
A.G.P. Bus Request: Used to request access to the bus to initiate an A.G.P.
A.G.P. request.
GGNT#
O
A.G.P.
A.G.P. Grant (additional information is provided on ST[2:0]): The additional
information indicates that the selected master is the recipient of previously
requested read data (high or normal priority). It is to provide write data (high or
normal priority) for a previously enqueued write command or has been given
permission to start an A.G.P. bus transaction .
GAD[31:0]
I/O
A.G.P. Address / Data: The standard address and data lines. Address is driven
A.G.P. with FRAME# assertion; data is driven or received in following clocks.
GC/BE[3:0]#
I/O
A.G.P.
A.G.P. Command / Byte Enables: For FRAME# protocol transactions, the
command is driven with FRAME# assertion. Byte enables corresponding to
supplied or requested data are driven on following clocks. The encoding is the
same as for PCI transactions.
Provides command information (different commands than PCI) when requests
are being enqueued using PIPE#. These signals provide valid byte information
during A.G.P. write transactions and is driven by the master. The target drives
“0000” during the return of A.G.P. read data and is ignored by the A.G.P.
compliant master.
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