82443LX Datasheet, PDF (81/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
when the CPU bus A16# address signal is asserted. A16# is asserted on the CPU bus when an I/O access is
made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is
made to 2 bytes from address 0FFFFh.
The I/O accesses (other than addresses for PCI configuration space access) are forwarded normally to the
PCI bus, unless they are in the A.G.P. I/O address range as defined by the following mechanisms.
A.G.P. Address Mapping
PAC directs I/O accesses to the A.G.P. port if they fall within the A.G.P. I/O address range. This range is
defined by the A.G.P. I/O Base Register (AIOBASE) and A.G.P. I/O Limit Register (AIOLIMIT). Decode for
these ranges is based on the following concept:
The top 4 bits of the I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address.
For the purpose of address decoding, PAC assumes that the lower 12 address bits A[11:0] of the I/O base
are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces I/O address range to be
aligned to 4-KB boundary and to have a size granularity of 4 KB. The address range covered by these
registers is defined by the following equation:
Base_Address ≤ Address ≤ Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and depends on
the size of I/O space claimed by the A.G.P. device. PAC also forwards accesses to the Legacy VGA I/O
ranges as defined and enabled by the “virtual” PCI-to-PCI bridge BCTRL and PCICMD1 configuration
registers.
Address Mapping of PCI Devices on A.G.P.
The same A.G.P. I/O range is also used to allocate an I/O address range for the PCI device (i.e., agent
attached to the A.G.P. port). The same applies in the case of a multi-functional A.G.P. device where one or
more of the functions are implemented as PCI-only devices.
4.1.5. PAC DECODE RULES AND CROSS-BRIDGE ADDRESS MAPPING
The address map described above applies globally to accesses arriving on any of the three interfaces
(i.e., Host bus, PCI, or A.G.P.).
4.1.5.1.
PCI Interface Decode Rules
PCI accesses in the PCI range are not accepted. Accesses that do not fall within the PCI range but are within
main memory, the A.G.P. range, or the Graphics Aperture range, are forwarded as described above. Note
that only PCI memory write accesses within A.G.P. Memory Window ranges (which do not overlap with
Graphics Aperture range) are forwarded to A.G.P. PCI cycles that are not claimed by PAC are either
subtractively decoded or master-aborted on the PCI.
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