82443LX Datasheet, PDF (22/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 3. PCI Interface Signals
Name
Type
Description
PCI Arbitration Signals
PHLD#
I PCI Hold: This signal comes from the PIIX4. It is the PIIX4 request for PCI bus
PCI ownership. PAC will flush and disable the CPU to PCI write buffers before granting
the PIIX4 the PCI bus via PHLDA#. This ensures prevention of a bus deadlock
condition between PCI and ISA.
PHLDA#
O PCI Hold Acknowledge: This signal is driven by the PAC to grant PCI bus
PCI ownership to the PIIX4 after CPU to PCI post buffers have been flushed and
disabled.
WSC#
O Write Snoop Complete: This signal is asserted active to indicate that all of the
PCI snoop activity on the host bus on the behalf of the last PCI to DRAM write
transaction (from PIIX4) is complete and that an APIC interrupt message can be
sent.
NOTE
1. This signal is used only in configurations where an I/O APIC is installed.
2. In non-APIC configurations, the WSC# mechanism can be completely
disabled by bit 15 of the PACCFG register.
REQ[4:0]#
I PCI Bus Request: REQ[4:0]# are the PCI bus request signals used as inputs by
PCI the internal PCI arbiter. If any of the REQ[x]# signals are NOT used, these inputs
must be pulled up to VCC3.
GNT[4:0]#
O PCI Grant: GNT[4:0]# are the PCI bus grant output signals generated by the
PCI internal PCI arbiter.
NOTES:
All PCI interface signals conform to the PCI specification, Revision 2.1.
2.1.4. A.G.P. INTERFACE SIGNALS
The A.G.P. interface consists of a set of signals similar to PCI called A.G.P. FRAME# Protocol signals. In
addition, there are 16 new signals added that constitute the A.G.P. sideband interface. The sections below
are organized in five groups: 1.) A.G.P. Sideband Addressing Signals, 2.) A.G.P. Sideband Flow Control
Signals, 3.) A.G.P. Sideband Status Signals, 4.) A.G.P. Sideband Clocking Signals (Strobes), and 5.) A.G.P.
FRAME# Protocol Signals.
Table 4. A.G.P. Signals
Name
Type
Description
A.G.P. Sideband Addressing Signals¹
PIPE#
I
A.G.P.
Pipelined Operation: PIPE# is asserted by the current master to indicate a full
width address is to be queued by the target. The master queues one request
each rising clock edge while PIPE# is asserted. When PIPE# is negated, no
new requests are enqueued across the AD bus.
PIPE# is a sustained tri-state signal from a master (graphics controller) and is
an input to the PAC.
SBA[7:0]
I
Sideband Address bus: SBA[7:0] provide an additional bus to pass addresses
A.G.P. and commands to the PAC from the A.G.P. master.
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