82443LX Datasheet, PDF (36/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.3.3. PCICMD—PCI COMMAND REGISTER (DEVICE 0)
Address Offset:
Default:
Access:
04–05h
0006h
Read/Write
This 16-bit register provides basic control over PAC’s PCI interface ability to respond to PCI cycles. The
PCICMD Register enables and disables the SERR# signal, parity checking (PERR# signal), PAC response to
PCI special cycles, and enables and disables PCI bus masters’ accesses to main memory.
Bit
Description
15:9 Reserved.
8 SERR# Enable (SERRE).
1=PAC’s SERR# signal driver is enabled and SERR# is asserted for all relevant bits set in the
ERRSTS and PCISTS as controlled by the corresponding bits of the ERRCMD register.
0=SERR# is never driven by PAC. SERR# is asserted under the following conditions:
1. PAC can assert SERR# when it is configured for ECC operation and a single bit
(correctable) ECC error, multiple bit (non-correctable) ECC error, or a DRAM parity error
occurred. ECC error signaling is enabled via the ERRCMD register (90h, Function 0).
2. PAC asserts SERR# when it detects a target abort during a PAC-initiated PCI cycle.
3. PAC can also assert SERR# when a PCI parity error occurs during the address phase
as controlled by bits 8 and 6 of PAC’s PCICMD register.
4. PAC can assert SERR# when it samples PERR# asserted on the PCI bus. This
capability is controlled by bit 3 of the ERRCMD register.
NOTE
This bit only controls SERR# for the PCI bus (Device 0). Device 1 has its own SERRE bit
(PCICMD1 register) to control error reporting for bus conditions occurring on the A.G.P. bus.
7 Reserved.
6 Parity Error Enable (PERRE). PERRE controls PAC’s PCI interface response to the PCI parity
errors during the data phase when PAC receives the data (i.e., during reads on the PCI bus and
PAC is the initiator and during writes when PAC is a target on the PCI bus).
1=Parity errors are reported on the PERR# signal. Note that when PERRE=1, address parity is
reported via SERR# mechanism (if enabled via SERRE bit) and not via PERR# pin.
0=No parity errors are reported by PAC’s PCI interface via PERR# or SERR# signals. (Note that
other types of error conditions can be still signaled via SERR# mechanism.)
5:0 Reserved.
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