82443LX Datasheet, PDF (90/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
NOTES:
1. 2-bank SDRAM DIMMs.
2. 4-bank SDRAM DIMMs.
3. 1-GB memory array is achieved by using Double-Sided Buffered EDO DIMMs.
4. Single-Sided DIMMs only.
Supported DRAM Types
PAC supports both EDO (Extended Data Out) DRAM and SDRAM (Synchronous DRAM). PAC supports a
2-KB page size and page mode is always active. PAC supports ECC and non-ECC types of both EDO and
SDRAM.
Extended Data Out (or Hyper Page Mode) DRAM is designed to improve the DRAM read performance. The
EDO DRAM holds the memory data valid until the next CAS# falling edge. With EDO, the CAS# precharge
overlaps the memory data valid time. This allows CAS# to negate earlier while still satisfying the memory
data valid window time.
Synchronous DRAM (SDRAM), as the name suggests, is based on the synchronous interface between the
DRAM controller and DRAM components. RAS#, CAS#, WE#, and CS# are pulsed signals driven by the
DRAM controller and sampled by the DRAM components at the positive clock edge of an externally supplied
clock (synchronous to 66-MHz system clock).
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