82443LX Datasheet, PDF (103/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
4.7. Arbitration and Concurrency
PAC enhances system performance by providing a high level of concurrency (capability of running multiple
operations simultaneously). System buses, as key resources, are arbitrated independently. Independent
buses allow multiple transactions to be issued simultaneously. As long as transactions on the independently
arbitrated buses do not compete for the common resources, they can proceed in parallel.
PAC’s distributed arbitration model permits concurrency between the host bus, PCI bus, A.G.P. bus, and the
DRAM interface. The arbitration algorithms and policies are designed to fulfill particular requirements of the
agents sharing the resources. They may favor different aspects of system performance: low bus/resource
acquisition latency, optimized instantaneous peak bandwidth, optimized sustained bandwidth, etc.
For the PCI bus, PAC supports five PCI masters in addition to the PIIX4 I/O bridge (Figure 10).
REQ[4:0]#/GNT[4:0]# are used for the five PCI masters and PHLD#/PHLDA# are used for PIIX4.
PHLD#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
Primary
PCI Bus
Arbiter
PHLDA#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
PCI_ARB
Figure 10. PCI Bus Arbiter
The PCI arbiter is based on a round robin scheme. PAC PCI Master interface (i.e., the Host) competes for
PCI bus ownership only when it needs to perform CPU-to-PCI or A.G.P.-to-PCI transactions. Since most
CPU-to-DRAM and A.G.P.-to-DRAM accesses can occur concurrently with PCI traffic, they do not consume
PCI bandwidth. The PAC PCI arbiter uses a complete bus lock mechanism to implement PCI exclusive
access operations. The arbiter implements a fairness algorithm in compliance with the PCI Local Bus
Specification. The PCI arbiter’s bus parking policy allows the current PCI bus owner, except for the I/O
bridge, to maintain ownership of the bus as long as no request is present from any other agent.
Multi-Transaction Timer (MTT) Mechanism
The PAC PCI arbiter implements an additional control for providing a guaranteed slice of PCI bus bandwidth
for bus agents which perform accesses to fragmented blocks of data and/or have real-time data transfer
requirements. This mechanism is called the Multi-Transaction Timer (MTT).
The MTT is a programmable timer that facilitates a guaranteed time slot within which a PCI initiator can
execute multiple back-to-back transfers, within the same arbitration cycle, to nonconsecutive regions in
memory.
This capability, supported at the AGPset level, enables the implementation of lower cost peripherals. The
bandwidth guarantee permits the reduction of on-chip data buffering in peripherals used for multimedia and
similar applications (e.g., video capture subsystems, ATM interface, Serial Bus host controllers, RAID SCSI
controllers, etc.).
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