82443LX Datasheet, PDF (14/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
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2.1. PAC Signals
2.1.1. HOST INTERFACE SIGNALS
Table 1. Host Interface Signals
Name
Type
Description
A[31:3]#
I/O GTL+
Address Bus: A[31:3]# connect to the processor address bus. During host
cycles, the A[31:3]# are inputs. PAC drives A[31:3]# during snoop cycles on
behalf of PCI and A.G.P. initiators. Note that the address signals are inverted
on the CPU bus.
ADS#
I/O GTL+ Address Strobe: The CPU bus owner asserts ADS# to indicate the first of two
cycles of a request phase.
BPRI#
O GTL+
Priority Agent Bus Request: PAC is the only Priority Agent on the CPU bus.
This signal is used to obtain the ownership of the address bus. Unless the
HLOCK# signal was asserted, BPRI# has priority over symmetric bus requests
and causes the current symmetric owner to stop issuing new transactions.
BNR#
I/O GTL+ Block Next Request: Used to block the current request bus owner from issuing
a new request. This signal is used to dynamically control the CPU bus pipeline
depth.
CPURST#
O GTL+
CPU Reset. The CPURST# pin is an output from PAC. PAC generates this
signal based on the RSTIN# input signal (from PIIX4). The CPURST# allow the
CPU(s) to begin execution in a known state.
DBSY#
I/O GTL+ Data Bus Busy: Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER#
O GTL+ Defer: PAC will generate a deferred response. PAC will also use the DEFER#
signal to indicate a retry response on the CPU bus.
DRDY# I/O GTL+ Data Ready: Asserted for each cycle that data is transferred.
HD[63:0]# I/O GTL+ Host Data: These signals are connected to the CPU data bus. Note that the
data signals are inverted on the CPU bus.
HIT#
I/O GTL+ Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, the target may extend the snoop window by driving HIT# in
conjunction with HITM#.
HITM#
I/O GTL+ Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
It is also driven in conjunction with HIT# to extend the snoop window.
HLOCK#
I GTL+
Host Lock: HLOCK# provides a mechanism to insure that cycles on the Host
bus are atomic. All cycles initiated while HLOCK# is asserted are guaranteed
atomic. (i.e., no PCI or A.G.P.-snoopable access to DRAM is allowed when
HLOCK# signal is asserted by the CPU.)
HREQ[4:0]#
I/O GTL+
Request Command: Asserted during both clocks of request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second clock, the signals carry additional
information to define the complete transaction type.
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