82443LX Datasheet, PDF (74/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.4.20. BCTRL—PCI-PCI BRIDGE CONTROL REGISTER (DEVICE 1)
Address Offset:
Default:
Access:
3E–3Fh
0000h
Read/Write
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The
BCTRL provides additional control for the secondary interface (i.e., A.G.P.). It also provides bits that affect
the overall behavior of the “virtual” PCI-to-PCI bridge embedded within PAC (e.g., VGA compatible address
ranges mapping).
Bit
Description
15:11 Reserved.
10 Discard Timer Status.
1=Indicates that a delayed transaction has been discarded. When set, this bit can be cleared
by writing a 1 to it.
9 Secondary Discard Timer Enable.
1=Enable. Enables the Discard Timer for delayed transactions on the A.G.P. (initiated by the
A.G.P. agent using FRAME# protocol). The counter starts once the delayed transaction
request is ready to complete (i.e., read data is pending on the top of the A.G.P. outbound
queue). If the A.G.P. agent does not repeat the transaction before the counter expires after
1024 clocks (66 MHz), PAC will delete the delayed transaction from its queue and set the
Discard Timer Status bit.
0=Disable.
8:4 Reserved.
3 VGA Enable. Controls the routing of CPU-initiated transactions targeting VGA compatible I/O and
memory address ranges.
1=Enable. When enabled, PAC forwards the following CPU accesses to the A.G.P.:
• Memory accesses in the range 0A0000h to 0BFFFFh
• I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases—A[15:10] are not decoded)
When enabled, forwarding of these CPU issued accesses is independent of the I/O address
and memory address ranges defined by the base and limit registers. Forwarding of these
accesses is also independent of the settings of bit 2 (ISA Enable) of this register if this bit
is a 1.
0=Disable (default). VGA compatible memory and I/O range accesses are not forwarded to
A.G.P. unless they are mapped to A.G.P. via I/O and memory range registers defined above
(IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT), they are mapped to primary
PCI.
2 ISA Enable. Modifies the response by PAC to an I/O access issued by the CPU that targets ISA
I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
1=Enable. PAC blocks the forwarding of I/O transactions addressing the last 768 bytes in each
1-KB block to A.G.P. This occurs even if the addresses are within the range defined by the
IOBASE and IOLIMIT. Instead of going to A.G.P., these cycles are forwarded to primary PCI
where they are claimed by the ISA bridge.
0=Disable (default). All addresses defined by the IOBASE and IOLIMIT for the CPU I/O
transactions will be mapped on A.G.P.
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