82443LX Datasheet, PDF (87/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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RCSA&B[7:6]#
RCSA&B[5:4]#
RCSA&B[3:2]#
RCSA&B[1:0]#
SRAS0#/SCAS0#
SRAS1#/SCAS1#
SRAS2#/SCAS2#
SRAS3#/SCAS3#
CKE
CDQB[5&1]#
CDQA[7:0]#
MD[63:0]
MECC[7:0]
WE0#
WE1#
WE2#
WE3#
MAA[13:2]
INTEL 82443LX (PAC)
MAA[1:0]
MAB[1:0]
MEM_#1
Figure 5. Configuration #1 (Large Memory Array)
In memory configuration #1, a buffered copy of MA[13:2] will go to all 4 DIMM sockets. MAA[1:0] will go to
DIMM socket 1 and DIMM socket 2, and MAB[1:0] will go to DIMM socket 3 and DIMM socket 4. CDQA[7:0]#
will go to DIMM socket 1 and DIMM socket 2. CDQA[7,6,4-2,0]# will go to DIMM socket 3 and DIMM socket
4. CDQB[5&1]# will go to DIMM 3 and DIMM 4.
One CKE signal provided by PAC is buffered and connected to each DIMM socket. Use a CMOS buffer to
provide copies of the CKE signal. four copies of the WE# signal are provided by PAC, and one is connected
to each DIMM socket.
The signal connections shown will support both EDO DRAM and SDRAM in the same memory array.
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