82443LX Datasheet, PDF (116/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 25. DRAM INTERFACE TIMING, 66 MHz (Configuration #2)
Functional Operating Range (VTT = 1.5V ± 10%, Vcc = 3.3V ±5%; TCASE = 0oC to +100oC)
Symbol
Parameter
Min
Max Units Figure Notes
t20 WE# Valid Delay from HCLKIN Rising
1.5
7.0
ns
17
0 pF
t21 MAA[13:0]#, MAB[13:0]# Valid Delay from
1.5
7.0
ns
HCLKIN Rising, SDRAM Read/Write cycles
17
0 pF
t22 SRAS[2:0]#, SRAS[3]#/MAB[5] Valid Delay
1.5
7.0
ns
from HCLKIN Rising
17
0 pF
t23 SCAS[2:0]#, SCAS[3]#/MAB[4] Valid Delay
1.5
7.0
ns
17v
0 pF
from HCLKIN Rising
t24 RCSA[5:0]#, RCSA[7:6]#/MAB[3:2],
RCSB[7:0]#/MAB[13:6] Valid Delay from
HCLKIN Rising
1.5
7.0
ns
17
0 pF
t25 CDQA[7:0]#, CDQB[1]#, CDQB[5]# Valid
Delay from HCLKIN Rising
1.5
6.5
ns
17
0 pF
t26 MD[63:0], MECC[7:0] Valid Delay from
HCLKIN Rising
1.0
6.0
ns
17
0 pF
t27 MD[63:0], MECC[7:0] Setup Time to HCLKIN 1.0
Rising
ns
18
note1
t28 MD[63:0], MECC[7:0] Hold Time from
2.0
HCLKIN Rising
ns
18
note1
t29 CKE Valid Delay from HCLKIN Rising
1.5
7.0
ns
17
0 pF
NOTES:
1. When EDO is driving, this specification is based on a 100pF load. When SDRAM is driving,
this specication is based on a 50pF load.
Table 26. PCI CLOCK TIMING, 33 MHz
Functional Operating Range (VTT = 1.5V ± 10%, Vcc = 3.3V ± 5%; TCASE = 0oC to +100oC)
Symbol
Parameter
Min
Max Units Figure Notes
t30 PCLKIN Period
30
ns
16
t31 PCLKIN Period Stability
500
ns
ps
t32 PCLKIN High Time
12.0
ns
16
t33 PCLKIN Low Time
12.0
ns
16
t34 HCLKIN Lead Time to PCLKIN
1
6
ns
t35 PCLKIN Rise Time
3.0
ns
16
t36 PCLKIN Fall Time
3.0
ns
16
116