82443LX Datasheet, PDF (125/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
Possible
Valid
Setting
Table 32. EDO Timing Performance Summary
Affect leadoff
RCD ¹
MAWS ⁵
RPT ⁶
1(2 clocks) 1(fast) 1(3 clocks)
0(3 clocks) 0(slow) 0(4 clocks)
Leadoff Clock Count
First Leadoff Pipeline
(PH/RM²/RM³/
PM)
Leadoff
(PH/RM³/PM)
Burst Clock Count ⁴
Read
Write
a
0
1
1
8/10/11/13
2/6/8
222 or 333 222 or 333
b
0
1
0
8/10/11/14
2/6/9
222 or 333 222 or 333
c
0
0
1
9/12/13/15
3/7/9
222 or 333 222 or 333
d
0
0
0
9/12/13/16
3/7/10 222 or 333 222 or 333
NOTES:
1. RAS to CAS delay, RCD (bit 1 of Register DRAMT), is always set to 0 for a 3 clock delay to have a
positive tRAC margin.
2. Row miss numbers assume that no RAS# is currently active .
3. One more clock should be added if the current RAS# has to be negated and the new RAS# has to be
asserted.
4. The EDO burst timing is also determined by the setting DRAMT bits [3,4].
5. MAWS is the EDO Memory Address Wait State. The setting of MAWS affects all cases. When MAWS is
set to 0 (slow), an extra clock is added for each CAS# and RAS# assertion.
6. RPT is EDO RAS Precharge time. This only affects a page miss.
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