82443LX Datasheet, PDF (41/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.3.12. PACCFG—PAC CONFIGURATION REGISTER (DEVICE 0)
Offset:
Default:
Access:
50–51h
0s00_s000_0000_0s00b
Read/Write, Read Only
PACCFG is a 16-bit register that is used for indicating the system level configuration
Bit
Description
15 WSC# Handshake Disable—R/W. This bit disables the internal WSC# handshake mechanism
for the configurations in which an I/O APIC is NOT used as a system interrupt controller.
1=Disable.
0=Enable (default).
14 Host Frequency—RO. This bit reflects the value of strap attached to the MECC0 pin. Information
stored in this bit is used by the DRAM refresh circuitry to select an optimum refresh count and
also by the BIOS to display the system bus frequency.
1=60 MHz.
0=66 MHz.
13:12 Reserved.
10 PCI Agent to Aperture Access Disable—R/W. This bit is used to prevent access to the aperture
from the primary PCI side (i.e., PAC’s PCI interface does not respond as a target with DEVSEL# if
the access is within the aperture). This bit is don’t care if bit 9 is 0.
1 = Disable.
0 = Enable. If this bit is 0 (default) and bit 9 of this register is 1, then accesses to the aperture
are enabled for the primary PCI side.
9 Aperture Access Global Enable—R/W. This bit is used to prevent access to the aperture from
any port (CPU, PCI or A.G.P.) before aperture range is established by the configuration software
and appropriate translation table in the main DRAM has been initialized.
1=Enable. It must be set after the system is fully configured for aperture accesses.
0=Disable (Default).
NOTE
This bit globally controls accesses to the aperture and that bit 10 provides the next level of
control for accesses originated from the primary PCI side.
8:7 DRAM Data Integrity Mode (DDIM)—R/W. These bits provide software configurability of
selecting between ECC mode, EC-only (error checking only) mode, or non-ECC mode of
operation of the DRAM interface in the following manner:
DDIM
00
01
10
11
DRAM Data Integrity Mode
Non-ECC (Byte-Wise Writes supported) (Default)
EC-only—Checking with No correction
reserved
ECC Generation and Checking/Correction
6 ECC_TEST Diagnostic Mode Enable (ETPDME)—R/W.
1=Enable. PAC enters an ECC Diagnostic test mode.
0=Disable (default). Normal mode.
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