82443LX Datasheet, PDF (62/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.3.29. AGPSTAT—A.G.P. STATUS REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
A4–A7h
1F000203h
Read/Write, Read Only
This register provides control of the A.G.P. operational parameters and reports A.G.P. device
capability/status.
Bit
31:24
23:10
9
8:2
1:0
Description
A.G.P. Request Queue Depth—RO. This field contains the maximum number of A.G.P.
command requests PAC is configured to manage. The lower 6 bits of this field reflect the value
programmed in A.G.P.CTRL[12:10]. Only discrete values of 32, 16, 8, 4, 2 and 1 can be selected
via A.G.P.CTRL. Upper bits are hardwired to 0. Default=1Fh
Reserved.
A.G.P. Side Band Addressing Supported. Hardwired to 1.
1=Indicates that PAC supports side band addressing.
Reserved.
A.G.P. Data Transfer Rates Supported. Hardwired to 11b. This field indicates the data transfer
rates supported by PAC. Note that this field applies to both AD bus and SBA bus.
11=Bit 0=1X, Bit 1=2X. Both 1x and 2x clocking are supported by PAC.
3.3.30. AGPCMD—A.G.P. COMMAND REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
A8–ABh
00000000h
Read/Write
This register reports A.G.P. device capability/status.
Bit
Description
31:10 Reserved.
9 A.G.P. Side Band Enable.
1=Enable
0=Disable (Default)
8 A.G.P. Enable.
1=Enable. When this bit is set to a 0, PAC ignores all A.G.P. operations, including the sync
cycle. Any A.G.P. operations received (queued) while this bit is 1, will be serviced even if
this bit is subsequently reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the
middle of an SBA command being delivered in 1X mode, the command will be serviced.
When this bit is set to a 1, PAC responds to A.G.P. operations delivered via PIPE#. In
addition, when this bit is set to a 1, PAC responds to A.G.P. operations delivered via SBA,
if the A.G.P. Side Band Enable bit is also set to 1.
0=Disable (Default)
7:2 Reserved.
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