82443LX Datasheet, PDF (70/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.4.13. IOBASE—I/O BASE ADDRESS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
1Ch
F0h
Read/Write
This register controls the CPU to A.G.P. I/O access routing based on the following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are treated
as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
Bit
Description
7:4 I/O Address Base. Corresponds to A[15:12] of the I/O address. Default=1111b
3:0 Reserved.
3.4.14. IOLIMIT—I/O LIMIT ADDRESS REGISTER (DEVICE 1)
Address Offset:
Default Value:
Access:
1Dh
00h
Read/Write
This register controls the CPU to A.G.P. I/O access routing based on the following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.
Bit
Description
7:4 I/O Address Limit. Corresponds to A[15:12] of the I/O address. Default=0000b
3:0 Reserved.
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