82443LX Datasheet, PDF (39/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
3.3.8. MLT—MASTER LATENCY TIMER REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
0Dh
00h
Read/Write
MLT is an 8-bit register that controls the amount of time PAC, as a PCI bus master, can burst data on the PCI
Bus. The count value is an 8-bit quantity. However, MLT[2:0] are 0 when determining the count value. PAC’s
MLT is used to guarantee to the PCI agents (other than PAC) a minimum amount of the system resources.
Bit
Description
7:3 Master Latency Timer Count Value for PCI Bus Access. The number of clocks programmed in
the MLT represents the guaranteed time slice (measured in PCI clocks; 33 MHz for standard PAC
configurations) allotted to PAC, after which it must complete the current data transfer phase and
surrender the bus as soon as its bus grant is removed. For example, if the MLT is programmed to
18h, the value is 24 PCI clocks. The default value of MLT is 00h and disables this function.
2:0 Reserved.
3.3.9. HDR—HEADER TYPE REGISTER (DEVICE 0)
Offset:
Default:
Access:
0Eh
00h
Read Only
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Description
7:0 Header Type. This read only field always returns 0 when read and writes have no effect.
3.3.10. APBASE—APERTURE BASE CONFIGURATION REGISTER (DEVICE 0)
Offset:
Default:
Access:
10−13h
00000008h
Read/Write, Read Only
The APBASE is a standard PCI Base Address register that is used to request the size of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration register in the
way that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or
behave as hardwired to 0). To allow for flexibility, an additional register called APSIZE is used as a
“back-end” register to control which bits of the APBASE will behave as hardwired to 0.
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