82443LX Datasheet, PDF (1/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 440LX AGPSET: 82443LX PCI
A.G.P. CONTROLLER (PAC)
T Supports the Pentium^® II Processor at
a Bus Frequency of 66 MHz
 Supports 32-Bit Addressing
 Optimized In-Order and Request
Queue
 Full Symmetric Multi-Processor
(SMP) Protocol for Up to Two
Processors
 Dynamic Deferred Transaction
Support
 GTL+ Compliant Host Bus
Supports WC Cycles
T Integrated DRAM Controller
 EDO (Extended Data Out), and
Synchronous DRAM Support
 Supports a Maximum Memory Size
of 512 MB With SDRAM, or 1 GB
With EDO
 64/72-bit Path to Memory
 Configurable DRAM Interface
 Support for Auto Detection of
Memory Type: (DIMM Serial
Presence Detect)
 8 RAS Lines Available
 Support for 4-, 16- and 64-Mbit
DRAM devices
 Support for Symmetrical and
Asymmetrical DRAM Addressing
 Configurable Support for ECC/EC
 ECC With Single Bit Error
Correction and Multiple Bit Error
Detection
 Read-Around-Write Support for
Host and PCI DRAM Read Accesses
 Supports 3.3V DRAMs
T Accelerated Graphics Port (A.G.P.)
Interface
 A.G.P. Specification Compliant
 A.G.P. 66/133 MHz 3.3V Devices
Supported
 Synchronous Coupling to the Host
Bus Frequency
T PCI Bus Interface
 PCI Revision 2.1 Interface
Compliant
 Greater Than 100-MBps Data
Streaming for PCI-to-DRAM
Accesses
 Integrated Arbiter With Multi-
Transaction PCI Arbitration
Acceleration Hooks
 Five PCI Bus Masters are Supported
in Addition to the Host and PCI-to-
ISA I/O Bridge
 Delayed Transaction Support
 PCI Parity Checking and Generation
Support
T Data Buffering For Increased
Performance
 Extensive CPU-to-DRAM, PCI-to-
DRAM, and A.G.P.-to-DRAM Write
Data Buffering
 CPU-to-A.G.P., PCI-to-A.G.P., and
A.G.P.-to-PCI Data Buffering
 Write Combining Support for
CPU-to-PCI Burst Writes
 Supports Concurrent Host, PCI, and
A.G.P. Transactions to Main
Memory
T System Management Mode (SMM)
Compliant
T 492 Pin BGA Package
The 82443LX (PAC) is the first generation of desktop AGPset designed for the Pentium^® II processor. The
82443LX PCI A.G.P. Controller (PAC) integrates a Host-to-PCI bridge, optimized DRAM controller and data
path, and an Accelerated Graphics Port (A.G.P.) interface. A.G.P. is a high performance, component level
interconnect, targeted at 3D graphics applications and based on a set of performance enhancements to PCI.
The I/O subsystem portion of the PAC platform is based on the PIIX4, a highly integrated version of the
Intel’s PCI-to-ISA bridge family. PAC is developed as the ultimate Pentium II processor platform and is
targeted for emerging 3D graphics and multimedia applications. The 440LX AGPset may contain design
defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
January 1998
Order Number: 290564-002