82443LX Datasheet, PDF (92/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
4.3.2. DRAM ADDRESS TRANSLATION AND DECODING
The 82443LX translates the address received on the host bus to an effective memory or PCI address. This
translation takes into account memory holes and the normal host to memory or A.G.P./PCI address. PAC
supports a maximum of 64-Mbit DRAM device. PAC supports the DRAM page size of the smallest density
DRAM that can be installed in the system. For 72-bit DIMMs, the overall DRAM DIMM page size is 8 KB. The
page offset address is driven over MA[8:0] when driving the column address. MAx[13:0] are translated from
the address lines A[26:3] for all memory accesses. The multiplexed row/column address to the DRAM
memory array is provided by the MAx[13:0] signals. The MAx[13:0] bits are derived from the host address
bus, as defined by Table 15, for symmetrical and asymmetrical DRAM devices.
Table 15. DRAM Address Translation
Memory Address
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row Row A24 A23 A12 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A11
Size
8 MB Col_s
A12 P
A10 A9 A8 A7 A6 A5 A4 A3
Col_e A24 A23 A26 A12 A22 A12 A10 A9 A8 A7 A6 A5 A4 A3
16 MB Col_s
A12 P
A23 A10 A9 A8 A7 A6 A5 A4 A3
Col_e A24 A23 A26 A12 A12 A23 A10 A9 A8 A7 A6 A5 A4 A3
32 MB Col_s A24 A23 A12 P
A24 A23 A10 A9 A8 A7 A6 A5 A4 A3
Col_e A24 A23 A26 A12 A24 A23 A10 A9 A8 A7 A6 A5 A4 A3
64 MB Col_s A24 A23 A12 P
A26 A25 A10 A9 A8 A7 A6 A5 A4 A3
Col_e A24 A23 A26 A25 A24 A23 A10 A9 A8 A7 A6 A5 A4 A3
128 MB Col_s A24 A23 A12 P
A26 A25 A10 A9 A8 A7 A6 A5 A4 A3
Col_e A24 A23 A26 A25 A24 A23 A10 A9 A8 A7 A6 A5 A4 A3
NOTES:
Col_s=SDRAM Column Address Mapping. Col_e=EDO Column Address Mapping. P=denotes the pre-charge
bit for SDRAM.
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