82443LX Datasheet, PDF (105/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
PCIREQ[4:0]#
PAC
REQ[4:0]#
GNT[4:0]#
WSC#
PHLD#
PHLDA#
PCI
PIIX4
PHLD#
PHLDA#
APICREQ#
APICACK#
PCIGNT[4:0]#
I/O APIC
APICACK2#
APICREQ#
APICACK1#
Figure 12. PAC and PIIX4 with an I/O APIC
PACPXAP
4.8. System Clocking and Reset
4.8.1. HOST FREQUENCY SUPPORT
The Pentium II processor uses a clock ratio scheme where the host bus clock frequency is multiplied by a
ratio to produce the processor’s core frequency. PAC supports a host bus frequency of 66 MHz. The external
synthesizer is responsible for generating the host clock. The Pentium II processor samples four signals:
LINT[1:0], (INTR, NMI), IGNNE#, and A20M# on the inactive to active edge of RESET to set the ratio.
4.8.2. CLOCK GENERATION AND DISTRIBUTION
PAC receives two outputs of a clock synthesizer on the HCLKIN and PCLKIN pins. PAC uses these signals
to clock internal logic and provide clocking control to PAC’s interfaces.
The clock skew between two host clock outputs of the synthesizer must be less than 250 ps (@1.25V). The
clock skew between two PCI clock outputs of the synthesizer must be less than 500 ps (@1.5V). In addition,
the host clocks should always lead the PCI clocks by a minimum of 1 ns and a maximum of 4 ns. PAC
requires a 45%/55% maximum output duty cycle. A maximum of 250 ps jitter must be maintained on the host
clocks going from cycle to cycle.
PAC does not support stopping of the HCLKIN or PCLKIN clock signals during operation. If either clock is
stopped, the PAC must be reset to ensure proper operation.
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