82443LX Datasheet, PDF (88/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Configuration #2: Enables small memory arrays (up to 6 rows) with two copies of Memory Address signals.
Three SRAS#, SCAS# and WE# signals are provided to support 3 DS DIMM sockets. This configuration
supports Single-Sided and Double-Sided x8 and x16 DIMMs. The Configuration #2 interface signals are
shown in Figure 6.
RCSA[1:0]#
RCSA[3:2]#
RCSA[5:4]#
SRAS0#/SCAS0#
SRAS1#/SCAS1#
SRAS2#/SCAS2#
CKE
WE2#
WE1#
WE0#
MECC[7:0]
MD[63:0]
CDQA[7:6,4:2,0]#
CDQB[5&1]#
CDQA[5&1]#
MAB[13:0]
MAA[13:0]
MEM_#2
Figure 6. Configuration #2 (Small Memory Array)
In memory configuration #2, MAB[13:0] are connected to the closest DIMM socket to PAC. MAA[13:0] is
connected to DIMM sockets 2 and 3. No external buffering is needed on the memory control and address
signals.
One CKE signal provided by PAC is buffered and connected to each DIMM socket. Use a CMOS buffer to
provide copies of the CKE signal. three copies of the WE# signal are provided by PAC, and one is connected
to each DIMM socket.
The signal connections shown will support both EDO DRAM and SDRAM in the same memory array.
Table 14 provides a summary of the characteristics of memory configurations supported by PAC. Minimum
values listed are obtained with single-density DIMMs and maximum values are obtained with double-density
DIMMs. The minimum values used are also the smallest upgradable memory size.
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