82443LX Datasheet, PDF (57/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Bit
Description
5 SERR# on Access to Invalid Graphics Aperture Translation Table Entry.
1=Enable. When bit 5=1 and access to an invalid entry of the Graphics Aperture Translation
Table stored in the main DRAM occurs, then bit 0 of the ERRSTS1 register will be set and
SERR# will be asserted.
0=Disable (default). Recommended programming value.
NOTE
The processor may do a speculative read to the aperture area that could hit an invalid entry
in the Graphics Aperture Remapping Table Entry. Since the code actually did not want this
data, the entry at this location may or may not be valid. If the entry happens to be invalid and
the bit that generates SERR# on access to invalid Graphics Aperture Translation Table Entry
(ERRCMD Register, Address Offset 90h, Bit 5) is enabled, then PAC will generate SERR#.
This spurious generation of SERR# could result in unwanted error messages and/or system
hangs. Disabled is the recommended value of this bit.
4 SERR# on receiving target abort.
1=Enable. PAC asserts SERR# upon receiving a target abort on either the Primary PCI or
A.G.P.
0=Disable. PAC does not assert SERR# upon receipt of a target abort (default).
3 SERR# on PCI Parity Error.
1=Enable. PAC asserts SERR# upon sampling PERR# or GPERR# asserted.
0=Disable. PAC does not assert SERR# upon receipt of a parity error via the PERR# or
GPERR# pins (default).
2 Reserved.
1 SERR# on Receiving Multiple-Bit ECC/Parity Error.
1=Enable. PAC asserts SERR# when it detects a multiple-bit error or parity error reported by
the DRAM controller. For systems not supporting ECC, this function must be disabled
(bit 1=0).
0=Disable.
0 SERR# on Receiving Single-bit ECC Error. When this bit is
1=Enable. PAC asserts SERR# when it detects a single-bit ECC error.
0=Disable.
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