82443LX Datasheet, PDF (4/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
CONTENTS
PAGE
1.0. OVERVIEW..............................................................................................................................................9
2.0. SIGNAL DESCRIPTION ........................................................................................................................ 13
2.1. PAC Signals ....................................................................................................................................... 14
2.1.1. HOST INTERFACE SIGNALS ..................................................................................................... 14
2.1.2. DRAM INTERFACE SIGNALS..................................................................................................... 15
2.1.3. PCI INTERFACE SIGNALS ......................................................................................................... 20
2.1.4. A.G.P. INTERFACE SIGNALS..................................................................................................... 22
2.1.5. CLOCKS, RESET, AND MISCELLANEOUS SIGNALS ............................................................... 25
2.2. Power-Up/Reset Strapping Options .................................................................................................... 26
2.3. State of PAC Output and Bi-directional Signals During Hard Reset .................................................... 27
3.0. REGISTER DESCRIPTION.................................................................................................................... 29
3.1. Register Access ................................................................................................................................. 30
3.1.1. CONFADD—CONFIGURATION ADDRESS REGISTER............................................................. 30
3.1.2. CONFDATA—CONFIGURATION DATA REGISTER .................................................................. 31
3.1.3. CONFIGURATION SPACE MECHANISM ................................................................................... 31
3.1.3.1. Routing the Configuration Accesses to PCI or A.G.P. ........................................................... 31
3.1.3.2. PCI Bus Configuration Mechanism........................................................................................ 31
3.1.3.3. Mapping of Configuration Cycles on A.G.P. .......................................................................... 32
3.2. PCI Configuration Space (Device 0 and Device 1).............................................................................. 32
3.3. Register Set—Device 0 (Host-to-PCI Bridge) ..................................................................................... 35
3.3.1. VID—VENDOR IDENTIFICATION REGISTER (DEVICE 0) ........................................................ 35
3.3.2. DID—DEVICE IDENTIFICATION REGISTER (DEVICE 0) .......................................................... 35
3.3.3. PCICMD—PCI COMMAND REGISTER (DEVICE 0) ................................................................... 36
3.3.4. PCISTS—PCI STATUS REGISTER (DEVICE 0)......................................................................... 37
3.3.5. RID—REVISION IDENTIFICATION REGISTER (DEVICE 0) ...................................................... 38
3.3.6. SUBC—SUB-CLASS CODE REGISTER (DEVICE 0) ................................................................. 38
3.3.7. BCC—BASE CLASS CODE REGISTER (DEVICE 0).................................................................. 38
3.3.8. MLT—MASTER LATENCY TIMER REGISTER (DEVICE 0) ....................................................... 39
3.3.9. HDR—HEADER TYPE REGISTER (DEVICE 0).......................................................................... 39
3.3.10. APBASE—APERTURE BASE CONFIGURATION REGISTER (DEVICE 0) .............................. 39
3.3.11. CAPPTR—CAPABILITIES POINTER (DEVICE 0)..................................................................... 40
3.3.12. PACCFG—PAC CONFIGURATION REGISTER (DEVICE 0) .................................................... 41
3.3.13. DBC—DATA BUFFER CONTROL REGISTER (DEVICE 0) ...................................................... 42
3.3.14. DRT—DRAM ROW TYPE REGISTER (DEVICE 0) ................................................................... 43
3.3.15. DRAMC—DRAM CONTROL REGISTER (DEVICE 0) ............................................................... 44
3.3.16. DRAMT—DRAM TIMING REGISTER (DEVICE 0) .................................................................... 44
3.3.17. PAM—PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) (DEVICE 0) ................. 46
3.3.18. DRB—DRAM ROW BOUNDARY REGISTERS (DEVICE 0)...................................................... 48
4