82443LX Datasheet, PDF (52/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
3.3.21. MBSC—MEMORY BUFFER STRENGTH CONTROL REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
6C–6Fh
55555555h
Read/Write
This register programs the various DRAM interface signal buffer strengths, based on memory configuration
(Configuration #1 or Configuration #2), DRAM type (EDO or SDRAM), DRAM density (x4, x8, x16, or x32),
DRAM technology (16 Mb or 64 Mb), and rows populated.
Bit
Description
31:30
MAA[1:0] Buffer Strength. This field sets the buffer strength for MAA[1:0].
00=48 mA
01=42 mA
10=22 mA
11=Reserved
29:28
MECC[7:0] Buffer Strength. This field sets the buffer strength of the MECC pin.
00=42 mA
01=38 mA
10=33 mA
11=Reserved
27:26
MD[63:0] Buffer Strength. This field sets the buffer strength of the MD[63:0] pin.
00=42 mA
01=38 mA
10=33 mA
11=Reserved
25:24
RCSA[0]# & RCSB[0]#/MAB[6] Buffer Strength. This field sets the buffer strength for RCSA[0]#
& RCSB[0]#/MAB[6] pins.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
23:22
MAB[1:0] Buffer Strength. This field sets the buffer strength of the MAB[1:0] pin.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
21:20
MAA[13:2] Buffer Strength. This field sets the buffer strength of the MAA[13:2] pin.
00=48 mA
01=42 mA
10=22 mA
11=Reserved
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