82443LX Datasheet, PDF (13/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
2.0. SIGNAL DESCRIPTION
This section provides a detailed description of each signal for the PAC. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high
voltage level.
The terms “assertion” and “negation” are used extensively. This is done to avoid confusion when working with
a mixture of “active-low” and “active-high” signals. The term assert or assertion, indicates that the signal is
active, independent of whether that level is represented by a high or low voltage. The term negate, or
negation indicates that a signal is inactive.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
OD Open Drain Output pin. This pin requires a pull-up to an appropriate voltage
I/O Bi-directional input/output pin
The signal description also includes the type of buffer used for the particular signal:
GTL+
Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete details
PCI
PCI bus interface signals. These signals are compliant with the PCI 5.0V Signaling
Environment DC and AC Specifications
A.G.P.
A.G.P. interface signals. These signals are compatible with A.G.P. Signaling Environment DC
and AC Specifications
LVTTL Low Voltage TTL compatible signals. These are also 3.3V inputs and outputs.
Note that the Pentium II processor address and data bus signals are logically inverted signals. In other words,
the actual values are inverted of what appears on the Pentium II processor bus. All control signals follow
normal convention. A 0 (low voltage) indicates an active level if the signal is followed by # symbol, and a 1
(high voltage) indicates an active level if the signal has no # suffix.
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