82443LX Datasheet, PDF (17/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

E
INTEL 82443LX (PAC)
Signal
CDQA[7:0]#
CDQB1#
CDQB5#
SRAS[2:0]#
Table 2. DRAM Interface Signals
Type
Description
O Column Address Strobe (EDO): For EDOs, these signals are used to latch the
LVTTL column address into the memory array (CAS signals). They drive the DRAM array
directly without external buffering.
Input/Output Data Mask (SDRAM): These pins act as synchronized output
enables during read cycles and as byte enables during write cycles. In the case of
write cycles, byte masking functions are performed during the same clock that
write data is driven (i.e., 0 clock latency).
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
O
LVTTL
Extra Copy of Column Address Strobe 1 (EDO) / Input/Output Data Mask 1
(SDRAM): This is a copy of CAS1#/DQM1 signal. It is used to balance the loading
for CAS1#/DQM1 in the ECC memory configurations where this signal is double-
loaded.
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
O
LVTTL
Extra Copy of Column Address Strobe 5 (EDO) / Input/Output Data Mask 5
(SDRAM): This is a copy of CAS5#/DQM5 signal. It is used to balance the loading
for CAS5#/DQM5 in the ECC memory configurations where this signal is double-
loaded.
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
O
LVTTL
SDRAM Row Address Strobe (SDRAM): The SRAS[2:0]# signals are multiple
copies (for loading purposes) of the same logical SRASx signal used to generate
SDRAM command. These commands are encoded on SRASx/SCASx/WE
signals. When SRASx is sampled active at the rising edge of the SDRAM clock,
the row address is latched into the SDRAMs.
Same function for Configuration #1 and Configuration #2.
These signals have programmable buffer strengths for optimization under different
signal loading conditions.
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