82443LX Datasheet, PDF (56/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 12. SMRAM Space Cycles
SMRAME DLCK DCLS DOPEN Pentium II Processor SMM
Mode Request (0=active)
Code Fetch
0
X
X
X
X
PCI
1
0
0
0
0
DRAM
1
0
X
0
1
PCI
1
0
0
1
X
DRAM
1
0
1
0
0
DRAM
1
0
1
1
X
INVALID
1
1
0
0
0
DRAM
1
1
X
0
1
PCI
1
1
1
0
0
DRAM
Data Reference
PCI
DRAM
PCI
DRAM
PCI
INVALID
DRAM
PCI
PCI
3.3.24. ERRCMD—ERROR COMMAND REGISTER (DEVICE 0)
Address Offset:
Default Value:
Access:
90h
00h
Read/Write
This 8-bit register controls PAC responses to various system errors. The actual assertion of SERR# or
PERR# is enabled via the PCI Command register.
Bit
Description
7 SERR# on A.G.P. Non-snoopable access outside of Graphics Aperture.
1=Enable. When this bit is set to a 1, and bit 2 of the ERRSTS1 register transitions from a 0 to
a 1 (during an A.G.P. access to the address outside of the graphics aperture), then an
SERR# assertion event will be generated.
0=Disable (default) reporting of this condition.
6 SERR# on A.G.P. Non-snoopable Access to the Location Outside of Main DRAM Ranges
and Aperture Range.
1=Enable. When bit 6=1 and an A.G.P. agent generates an access using enhanced A.G.P.
protocol (i.e., PAC must accept the request without qualification with decode logic since
there is no protocol mechanism to reject it) and access is not directed to either main
memory range or the aperture range, then bit 1 of the ERRSTS1 register is set and SERR#
asserted.
0=Disable (default). When disabled, this condition is not reported via SERR#. PAC ignores
A[35:32] of SBA cycles, and therefore will not signal SERR# on accesses over 4G (unless
the alias below 4G does not fall within main DRAM or the aperture).
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