82443LX Datasheet, PDF (119/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
Table 29. A.G.P. INTERFACE TIMING,133 MHz
Functional Operating Range (VTT = 1.5V ± 10%, Vcc = 3.3V ± 5%; TCASE = 0oC to +100oC)
Symbol
Parameter
Min Max Untis Figures Notes
t59 ADSTBx falling Valid Delay at transmitter from
2
12 ns
HCLKIN rising.
22
tTSf,
note1,2, 3
t60 ADSTBx rising Valid Delay at transmitter from
HCLKIN rising.
20 ns
22
tTSr
t61 GAD[31:0],GC/BE[3:0]# Valid Delay before
1.7
ADSTBx Rise/Fall
ns
22
tDvb
t62 GAD[31:0] GC/BE[3:0]# Valid Delay after
1.7
ADSTBx Rise/Fall
ns
22
tDva
t63 GAD[31:0] GC/BE[3:0]# Float to Active Delay
-1
9
ns
from HCLKIN rising.
21
tOND
t64 GAD[31:0], GC/BE[3:0]# Active to Float Delay
1
12 ns
from HCLKIN rising.
21
tOFFD
t65 ADSTBx rising Delay Time at transmitter to
ADSTBx floating.
6
10 ns
21
tOFFS
t66 ADSTBx active Setup Time at transmitter to
ADSTBx falling.
6
10 ns
21
tONS
t67 ADSTBx rising Setup Time at receiver to
6
HCLKIN rising.
ns
22
tRSsu
t68 ADSTBx falling Hold Time at receiver to
1
HCLKIN rising.
ns
22
tRSh
t69 GAD[31:0],GC/BE[3:0]# Setup Time to ADSTBx 1
Rise/Fall
ns
22
tDsu
t70 GAD[31:0] GC/BE[3:0]# Hold Time from
1
ADSTBx Rise/Fall
ns
22
tDh
t71 SBSTB rising Setup Time at receiver to
6
HCLKIN rising.
ns
22
tRSsu
t72 SBSTB falling Hold Time at receiver to HCLKIN 1
rising.
ns
22
tRSh
t73 SBA[7:0] Setup Time at receiver to SBSTB
1
Rise/Fall
ns
22
tDsu
t74 SBA[7:0] Hold Time at receiver from SBSTB
1
Rise/Fall
ns
22
tDh
NOTES:
1. ADSTBx refers to ADSTBA and ADSTBB.
3. Specifications are based on a 10pF loading.
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