82443LX Datasheet, PDF (95/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)
4.3.5. SERIAL PRESENCE DETECT (SPD) FOR SDRAM
A Slot 1/440LX AGPset Platform requires the support of Serial Presence Detect (SPD) for SDRAM DIMMs in
the memory array. SPD is needed to gather specific DIMM information to program the Memory Buffer
Strength Control Register. This information is ONLY obtainable through Serial Presence Detect.
A 82443LX (PAC) memory subsystem is dependent on the type and size of DRAM in the array. To properly
program the DRAM Controller Registers, specific information is needed during Boot time. Information such as
DRAM size (x4, x8, or x16), will affect the values programmed in the Memory Buffer Strength Register
(Register 6C-6Fh, Device #0).
• Why is SPD needed? Previously, a BIOS algorithm could determine DRAM size and type dynamically.
Buffer strength programming was limited to memory address signals only, based on the number of rows
populated. In the PAC, every memory interface signal’s buffer strength is programmable. This allows the
PAC to support a wide range of DRAM types and sizes. To program these buffer strengths correctly, the
BIOS needs information on DRAM size. For example, signal loading is greater when the array is
populated with x4 DRAMs than x16 DRAMs. Thus, memory interface signal strengths will need to be
greater.
• Can SPD be Bypassed by disabling a row? This is not an option. If the BIOS detects a row of SDRAM
memory which does not support SPD, even if this row is disabled, signal loading from the non-SPD
SDRAM DIMM exists, and the MBSR can not be programmed reliably.
• Can an Error Message report a non-SPD DIMM? Video is initialized during BIOS post testing well after
DRAM is initialized. If the MBSR is not programmed properly, the BIOS post test will not make it far
enough to report the error to the screen.
The memory subsystem must be designed to support Serial Presents Detect to properly program the Memory
Buffer Strength Register. Also, ensure the SDRAM DIMMs used comply with the latest SPD JEDEC
Specification, revision: December, 1996
4.3.6. SINGLE CLOCK COMMAND MODE FOR SDRAM
The graphics subsystem will potentially require data transfers of less than or equal to one QWord (8 bytes)
per command consecutively during the memory access. One QWord is referred to a piece of data in a 64-bit
memory interface. With CAS latency (CLT) equal to 2, there will be a 2 clock (3 clock with CLT=3) delay
between the read command and data cycles. Without supporting single clock command mode, the system
will not be able to achieve 1111 effective burst rate for this type of data access pattern. As illustrated from
the following diagram, effective burst rate becomes 2222 with respect to the requested data if single clock
command mode is not enabled.
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