82443LX Datasheet, PDF (126/144 Pages) Intel Corporation – INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

INTEL 82443LX (PAC)
E
Table 33. SDRAM Timing Performance Summary
Possible
Valid Setting
Affects Leadoff
SCLT ¹
1(2 clocks)
0(3 clocks)
SRCD ²
1(2 clocks)
0(3 clocks)
SRPT ³
1(2 clocks)
0(3 clocks)
Leadoff Clock Count
First Leadoff
PH/RM⁴/RM⁵/
PM
Pipeline
Leadoff
PH/RM⁵/PM
Burst Clock
Count
Read & Write
a.
1
1
1
8/10/11/12
2/4/5
111
b
1
1
0
8/10/11/13
2/4/6
111
c
0
1
1
9/11/12/13
1/5/6
111
d
1
0
1
8/11/12/13
2/5/6
111
e
0
1
0
9/11/12/14
1/5/7
111
f
0
0
0
9/12/13/15
1/6/8
111
g
1
0
0
8/11/12/14
2/5/7
111
h
0
0
1
9/12/13/14
1/6/7
111
NOTES:
1. SCLT is SDRAM CAS Latency. The setting of SCLT affects all cases(page hit, page miss, and row miss).
2. SRCD is SDRAM RAS to CAS delay. The setting of this bit affects both page miss and row miss.
3. SRPT is SDRAM RAS precharge time. The setting of this bit affects only page miss.
4. Row miss numbers assume that no RAS# is currently active.
5. Row miss numbers assume that the current RAS# has to be negated and the new RAS# has to be
asserted.
6. The same MAWS control bit for EDO timing in register 58h of PAC (device 0) has a different timing effect
for SDRAM. All the clock counts are based on MAWS = 1 (fast). When MAWS = 0 (slow), an extra clock
is added before each CS# assertion.
Following are the waveforms illustrating the page hit, page miss and row miss with different settings of SCLT,
SRCD, SRPT, and MAWS=1.
126